Tag Archive SOC

ByGianni PRATA

Don’t miss EuroSOI-ULIS, 25-27 January 2016 in Vienna. Call for papers still open.

logo_eurosoi_ulisThe 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, aka EUROSOI-ULIS 2016 will be taking place January 25-27, 2016 in Vienna, Austria. The event will be hosted by the Institute for Microelectronics, TU Wien. The focus of the sessions is on SOI technology and advanced nanoscale devices. The organizing committee invites active participation and submission of high quality papers (the Paper Submission deadline has been extended until Dec. 14 2015).
EuroSOI is a conference that’s been going on for decades. Many of the leading edge SOI technologies making headlines today were first presented here. This year’s conference features talks by top researchers from Europe and Japan, and a plenary talk from ON Semi entitled SOI technology for advanced power management: context and trends.
Click here for conference registration details.
ByAdministrator

FD-SOI Everywhere: GF & Samsung Videos, Press, Conferences and more – a quick roundup

Over the last few weeks there’s been another burst of activity in the FD-SOI arena. A new round of articles, videos and conferences are making FD-SOI the centerpieces. Here’s a quick round-up of things you won’t want to miss.

GlobalFoundries video

Info on GlobalFoundries 22nm FD-SOI offering just keeps on coming. Following the ASN roundup of info from the summer and fall (missed it? read it here), they’ve posted yet another excellent FD-SOI video:GF22_FDSOI_BodyBias_video

How to optimize power and performance with 22FDX™ Platform body-biasing – Dr. Jamie Schaeffer gives a quick (under 3 minute) guide to the basics of front and reverse body-biasing, and the GF approach to a dynamic trade-off between power and performance . He explains how forward body bias (FBB) boosts performance at both high and low voltages, and how reverse body bias (RBB) cuts leakage for the lowest standby power. He also touches on FBB techniques for analog/RF designs.

Samsung video

Samsung28FDSOI_runnersThey’re back! Though they’ve been pretty quiet recently, this latest Samsung video on their 28nm FD-SOI foundry offering hits right at the heart of IoT. Entitled The IoT Revolution and Samsung Foundry’s 28nm FD-SOI, the fun two-minute spot features two runners talking shop during a break. She asks: Is there a lot of design ecosystem support for FD-SOI? He answers: Absolutely. And he goes on to talk about the EDA/IP ecosystem they’re building. It ends on this tantalizing note: He: So you’re done? She: Not! Race you to the next station! He: Oh, it’s on!

SemiWiki.com

With reader interest high and higher, FD-SOI continues to get great coverage in SemiWiki.com. Here are some recent good reads:

IP-SoC Rebound in 2015 ! – IP expert Eric Esteve covers FD-SOI highlights from the upcoming IP-SOC 2015 conference in Grenoble, France (2-3 December 2015), including these presentations (full program here):

  • FDSOI is taking on speed as platform and a European focus project by Gerd Teepe, GlobalFoundries
  • FDSOI IP Shop: The key enabler of success by Patrick Blouet, Collaborative program manager, STMicroelectronics
  • Strategies for SoC / IP Design for Emerging Applications: An Indian perspective by Samir Patel, Sankalp Semiconductor
  • Assessing and managing the IP Sourcing Risk by Philippe Quinio, STMicroelectronics
  • Power Planning and Timing Signoff Solutions by SOI guru and ARM Fellow Jean-Luc Pelloie
  • FD-SOI a New Era for Power Efficiency: Why and How? By Olivier Thomas, Silicon Impulse, CEA – LETI (btw, if you missed his excellent ASN piece explaining Leti’s Silicon Impulse program, you can still read it here)

28nm FD-SOI: A Unique Sweet Spot Poised to Grow – Pawan Fangaria explains why “…today the 28nm FD-SOI technology node stands to win as the best value added proposition for the emerging markets such as IoT, automotive, consumer, mobile, and so on.”

Globalfoundries 22FDX Technology Shows Advantages in PPA over 28nm Node – Tom Simon was at ARM Techcon, where he attended a talk sponsored by Cadence on the topic of using GlobalFoundries 22nm FD-SOI process to implement a quad core ARM Cortex-A17. He shares a number of the key slides in this informative blog.

SemiEngineering

SemiEngineering Editor-in-Chief Ed Sperling continues his great line-up of incisive interviews. In Increasing Challenges At Advanced Nodes, he gets some spot-on FD-SOI quotes from GlobalFoundries CTO Gary Patton, including:

  • “It’s great that you get finFET performance at 28nm cost. But what’s really interesting for me is that you get software control. You can turn chips, blocks and circuits on and off. It’s a whole new degree of freedom for the designer.”
  • “ I believe 22nm FD-SOI fits the sweet spot.”
  • “We wouldn’t do 14nm FD-SOI. We would want a bigger jump than that. It would something closer to 10nm.[…] …it would be planar. If you go to finFET, you would lose the back body biasing. That’s a key attribute.”

ByGianni PRATA

Leading SOC Place-and-Route Tools Qualified for GF’s 22FDX; includes dynamic tuning

ATopTech, a leader in next-generation physical design solutions, has announced that their Aprisa™ and Apogee™ Place & Route tools are now enabled for the current version of the GlobalFoundries 22FDX™ platform reference flow. GF has qualified these tools for the 22FDX reference flow to provide customers with the design flexibility of using body bias to manage power, performance and leakage needed to create the next-generation chips for mainstream mobile, IoT and networking applications. (Read the press release here.)

ATopTech tools provide designers with the capability to intelligently and dynamically tune the power and performance of the next-generation system-on-chip (SoC) designs.

ByAdministrator

RF-SOI vs. FD-SOI with RF – What’s the difference?

Is RF-SOI the same thing as RF on FD-SOI? No, it’s not. However, the runaway success of RF-SOI and the growing list of recent announcements related to FD-SOI with integrated RF has lead to some confusion in the press and social media. The two are different technologies, addressing different markets, and built on two very different types of SOI wafers. The use of one technology or the other depends on the requirements of the targeted RF application.

For the non-technical reader, here is a bit of basic background. At the most simplistic level – RF: radio frequency – is part of the analog family, and as such is all about waves. And when you talk about waves, you talk about losses over distance (attenuation), speed, wavelength and frequency – which is why the RF design has a rep of being something of a black art. The distance to cover, the power envelope and the amount of data to carry over that distance (and of course, the cost) determine the chip solutions. An important part of the RF chip solution is the choice of the wafer substrate itself.

So here’s a quick primer to help sort out what’s what. Please bear in mind, though, that this is a fast-evolving world, so what you’re about to read is not a definitive and forever what’s what – but more of a general (and simplified) “this is how it is currently shaking out”.

RF-SOI – Talk to the Tower

When it comes to using your mobile device for data transmission over a 2G, 3G, 4G/LTE/LTE-A (and next, 5G) network, you still need dedicated RF front-end modules (FEMs). FEMs handle the back-and-forth of signals between the transceiver and the antenna. They contain multiple parts, including switches, power amplifiers, antenna tuning, power management and filters. Traditionally, they were built on gallium arsenide substrates. But more and more, the multiple chips in FEM chipsets are being reduced to single SOCs built on a special class of high-resistivity SOI wafers. This is the realm of RF-SOI. The wafers for RF-SOI are designed specifically to handle the special needs of getting a lot of data transmitted wirelessly, often over relatively long distances.

eSI_SoitecUCLwafer

Soitec premiered a radically new and immensely successful generation of RF-SOI substrates in 2013: the enhanced Signal Integrity™(eSI) family, which introduced the concept of the “trap-rich” layer developed at UCL. (Image courtesy of Soitec)

The latest standards (LTE-A and 5G) raise the stakes ever higher, requiring mobile devices to support more bands, higher frequency bands, and emission and reception on adjacent bands with downlink and uplink carrier aggregation. (Carrier aggregation refers to the simultaneous reception of multiple frequency bands to improve data throughput.)

For RF designers, that means choosing substrates that favor low RF loss and high RF linearity. A couple of years ago, SOI leader Soitec, in partnership with UCL, brought breakthrough RF-SOI wafer technology to the market (read about that here). Now, a few generations later, Soitec estimates that one billion RF devices are produced each quarter using their advanced and enhanced Signal Integrity™(eSI)wafers for RF. In fact it would be nigh near impossible to find a smartphone that doesn’t have an RF FEM based on  RF-SOI wafer technology.

Here at ASN, we’ve covered many of the leaders in RF-SOI FEMs over the last few years. Click on any of these names to get an idea of what they’re doing: IBM (now part of GlobalFoundries), Peregrine, SkyWorks, TowerJazz, ST, Qorvo, Sony, Qualcomm, Grace, Toshiba and MagnaChip. To learn more about the latest developments in wafer technology for RF-SOI, click here. With demand soaring, Soitec’s most advanced RF-SOI wafers are now also being produced by Simgui in China – read about that here.

In fact, the cover story and technical features of the October 2015 issue of the prestigious Microwave Journal is dedicated to RF-SOI – click here to read it.

So in terms of terminology, that’s “RF-SOI”. Now let’s look at how RF on FD-SOI is different.

RF in FD-SOI – for digital integration

When we talk about RF in FD-SOI, we’re typically talking about some RF functionality being integrated into SOCs that are essentially digital processors. True, you can integrate RF functionality into an SOC built on planar bulk (it’s generally agreed to be a nightmare in bulk FinFETs, though). But you can integrate RF into your digital SOC much more easily, efficiently and with less power if you do it in FD-SOI.

RF/analog has a (well-deserved) rep of being the most challenging part of chip design. Analog/RF devices are super sensitive to voltage variations. The digital parts of a chip, which have strong, sudden signal switching, can raise havoc with nearby analog/RF blocks. This means that the analog/RF designers have to care acutely about gain, matching, variability, noise, power dissipation, and resistance. They use all kinds of specialized techniques: FD-SOI makes their job a lot easier (good explanation in slide 8 here). What’s more, FD-SOI’s analog performance far exceeds bulk.

What sort of chips are we talking about? For now, we’re talking about processors for mobile devices, for IoT, for automotive, for consumer electronics. When we say “RF in an FD-SOI SOC”, we’re currently talking about chips that are connecting over a relatively short distance to a nearby box or device (<100m for local WiFi, or a few meters for Bluetooth or Zigbee, for example).

ST’s new set-top-box processors on 28nm FD-SOI (read about them here) are a great example. They are the first on the market integrating 4×4 802.11ac Wi-Fi (using IP from Quantenna) and High Dynamic Range support. This means the set-top boxes can reliably serve lots of HD video via WiFi to multiple users throughout the house (hopefully ending the cry: “Who’s hogging all the Wifi?!?”). ST credits their 28nm FD-SOI silicon technology with providing that highly-efficient RF, state-of-the-art WiFi performance and robustness required for reliable video delivery inside the home.

For RF on FD-SOI – as in other FD-SOI apps – designers use SOI wafers with ultra-thin silicon, ultra-thin insulating BOX and phenomenal top silicon thickness uniformity. These wafers are not the special high-resistivity wafers used in RF-SOI. Rather, they are the latest generations of the same (amazing!) FD-SOI wafers that Soitec introduced in 2010. (For an excellent, in-depth interview with the Soitec FD-SOI wafer guru on the supply chain and the most recent developments, click here.)

TopSiLoss_FDSOI

The top silicon uniformity of Soitec’s “FD-2D” wafers for FD-SOI is guaranteed to within +/-5Å at all points on all wafers. 5 Å across a wafer is equivalent to 5 mm over 3,000 km, which corresponds to approximately 0.2 inches over the distance between Chicago and San Francisco. That uniformity is maintained not just across each wafer, but from one wafer to the next. The BOX thickness is 10nm to 25nm, depending on the customer’s approach.

This is the type of wafers that GloFo, ST, Samsung, Freescale, Sony, several other companies in Japan and many more around the world are using when they say they’re doing RF on FD-SOI. Bear in mind that this level of SOC integration is fairly new (Samsung and TSMC just announced RF integration into SOCs for the first time in 2014 on 28bulk). But using FD-SOI technology and the corresponding ultra-thin SOI wafer substrates makes life much easier for the RF folks on the design teams, gets far better performance and far lower power at a much more attractive cost.

Further ahead, FD-SOI is also a candidate for transceivers and baseband/modem SOCs, which require high-performance digital and analog/RF integration. But even with transceivers on FD-SOI, you’ll still need the FEM on RF-SOI to handle the interface.

So, that’s the current difference between RF-SOI and RF on FD-SOI.

Hope that helps to clear things up?

ByAdministrator

GF’s 22nm FD-SOI Offering – Where to Get Lots of Excellent Info

A fast-growing body of information is now posted by GlobalFoundries on their new 22nm FD-SOI offering.

After years of asking “where’s FD-SOI on the GF website??”, it’s (finally!) there, front and center. There are some excellent new videos and documents. Here’s a rundown of what you’ll find.

GFwebsiteFDXintro

The 22FDX Platform introduction is the currently the lead topic on the GlobalFoundries website.

When you click down the “Technology Solutions” tab and select “Leading Edge Technologies”, here’s how they describe their 22nm FD-SOI offering:

GLOBALFOUNDRIES 22FDX™ platform employs 22nm Fully-Depleted Silicon-On-Insulator (FD-SOI) technology that delivers FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar technologies. While some applications require the ultimate performance of three-dimensional FinFET transistors, most wireless devices need a better balance of performance, power consumption and cost. 22FDX provides the best path for cost-sensitive applications. The 22FDX platform delivers a 20 percent smaller die size and 10 percent fewer masks than 28nm, as well as nearly 50 percent fewer immersion lithography layers than foundry FinFET.

  • Ultra-low power consumption with 0.4V operation
  • Software-controlled transistor body-biasing for flexible trade-off between performance and power
  • Integrated RF for reduced system cost and back-gate feature to reduce RF power up to ~50%
  • 70% lower power than 28HKMG

Here are some of the resources posted on the website as of this writing:

Product Brief: 22FDX™ – a two-page pdf summarizing the platform advantages, the various application-optimized offerings, and basic graphics explaining how body-biasing works and what advantages it provides

FD-SOI Technology Innovations Extend Moore’s Law (white paper) – NEW! Just posted in September 2015, this 8-page white paper covers the basics of the FD-SOI transistor, how body biasing works, the impact the technology has on common circuit blocks (digital, analog & RF, embedded SRAM), and the outlook for future scaling (which goes down to 10nm).

15-GFwebinarSept28_FDX_ULPSOCex

This slide is about 17 minutes into GF’s “How to build ULP chips with 22nm FD-SOI…” webinar.

Webinar: How to Build Ultra Low Power Chips with New 22nm FD-SOI TechnologyNEW! Just posted on September 24, 2015. GF’s Jamie Schaeffer, Ph.D. Leading Edge Product Line Manager is talking to designers here. After a brief overview (he looks at the features, the extensions, the IP suite, and so forth), he gets into the fundamentals of body biasing, the different transistor optimizations, specific advantages for RF & analog, the tools for ultra-low-power design, and what’s in the design starter kits that are available today. Total running time is just under 20 minutes.

GFwebsiteFDXJulyWebinarPPcost

This slide is shown about 12 minutes into GF’s “Extending Moore’s Law with FD-SOI” webinar.

Webinar: Extending Moore’s Law with FD-SOI Technology – this is the webinar Jamie Schaeffer gave with ChipEstimate.com the day of the company’s FD-SOI announcement in July 2015. It’s a fairly high level presentation: very useful for designers, but also accessible to those outside the design community. There’s a lot of background on FinFET vs. FD-SOI, cost comparisons, target apps, and actual results seen in silicon. It’s an especially good place to start if FD-SOI is new to you. It runs just over 35 minutes.

Tech Video: Benefits of FD-SOI Technologies – in this short video by Subi Kengeri, GF’s VP of the CMOS Platforms BU, he gives a quick rundown of the benefits of FD-SOI. It runs about 2 minutes.

Another excellent place to get more indepth info on FD-SOI is an interview with Subi Kengeri by SemiEngineering Editor-in-Chief Ed Sperling (click here to see it on YouTube). This video, entitled Tech Talk: 22nm FD-SOI, was made just after the July announcement. Subi really goes into substantial detail, and clearly explains the key differences between FinFETs and FD-SOI. He explains why FD-SOI has less variability than FinFETs, why FinFETs have higher device capacitance, and how only with FD-SOI can you dynamically change Vt. FD-SOI also comes out better in terms of dynamic power, thermal budget and RF integration. Highly recommended – it runs just over 20 minutes.

You might also want to check out GF CEO Sanjay Jha’s Shanghai FD-SOI Forum presentation, The Right Technology at the Right Time, on the SOI Consortium website. (There are lots of others there, too!) Taking a bird’s eye view of the semiconductor industry drivers and requirements, he concludes, “22FDX and RFSOI have the power, performance, and cost to drive growth in mobile, pervasive, and intelligent computing.”

Which is great news for the SOI ecosystem and the entire industry.

ByGianni PRATA

ST unveils first FD-SOI products – groundbreaking SOCs for set-top-boxes

FD-SOI champion STMicroelectronics has unveiled the company’s first System-on-Chip (SoC) products on FD-SOI. Two multi-core ARM SoC offerings – both for set-top boxes – have been announced. ST credits the 28nm FD-SOI silicon technology with providing highly-efficient RF and analog integration as well as outstanding power efficiency so that set-top box makers can now design very small fan-less systems. The announcements include:

  • The Cannes Wi-Fi (STiH390): the first set-top-box SoC on the market integrating 4×4 11ac Wi-Fi (using IP from Quantenna) and High Dynamic Range support. This delivers state-of-the-art Wi-Fi performance and robustness required for reliable video delivery inside the home. (Read the press release here.)
  • The new HD HEVC Liege3 family of chipsets for entry Set-Top-Box markets, with flavors for satellite, cable-market and IPTV set-top-box devices. More than just an upgrade of previous-generation devices, the new chipset family combines the latest architectures used in ST’s Cannes products with optimized IPs to deliver future-proof SoCs with high integration. ST says this will enable large-scale migration of entry set-top boxes towards HEVC (High Efficiency Video Coding). All chipsets are pin-to-pin compatible to facilitate design re-use among the different broadcast technologies. Software compatibility with ST’s Cannes SoC family enables OEMs to benefit from the comprehensive ecosystem in order to easily design innovative client boxes on multiple middleware products. (Read the press release here.)

Both are currently sampling to lead customers.

ByGianni PRATA

FD-SOI could account for half of GF’s Dresden fab by 2018 (EETimes); drives More-than-Moore to mainstream

In an interview with EETimes, GlobalFoundries CEO Sanjay Jha indicated that more than 50% of the Dresden fab output could be FD-SOI by 2018 (read it here). Jha also told EETimes that More-than-Moore technologies can be considered the mainstream. In the piece entitled, Can GloFo and Europe’s chip firms unite? author Peter Clarke makes an excellent point that between the four European chip leaders (NXP-Freescale, ST, Infineon and GF), “…there is the digital, RF, power, mixed-signal and microcontroller expertise to make almost any sort of wireless sensor node or any other circuit for the Internet of Things. What is clear is that there is no longer a single vector of excellence in integrated circuit manufacturing.” A recommended read.

ByGianni PRATA

ST 28nm FD-SOI SOC Design Throughput 10X faster with Synopsys Compiler II

Synopsys recently announce that its IC Compiler II place and route solution was used by STMicroelectronics to tape out a complex 28-nm-FD-SOI SoC. (Read the press release here.) Fast throughput and analysis delivered a 10X reduction in time-to-good-floorplan. A 5X faster implementation with 2X smaller memory footprint enabled breakthrough productivity while exceeding quality of results (QoR) in area, timing and power goals.

Thierry Bauchon, ST R&D Director, said, “Our experience proved the promise we saw early in the design with 10X faster design exploration and 5X faster implementation, enabling us to refine floorplans, up-size physical partitions and achieve faster clock speeds on this tapeout.”

ByGianni PRATA

RF-SOI Key in MagnaChip IoT Plans

RF-SOI will play a key role in the IoT plans of analog and mixed-signal specialist MagnaChip (read the press release here). The company has launched a task force to address IoT. The statement says, “MagnaChip also offers 0.18 micron and plans to offer 0.13 micron Silicon on Insulator (SOI) RF-CMOS technologies, which is suitable for use in antenna switching, tuner and Power Amplifier (PA) applications. Switches and tuners are core components of wireless Front-End-Modules (FEMs) for cellular and Wi-Fi connectivity in IoT devices. MagnaChip’s CMOS based FEMs reduce manufacturing cost and time to market while providing competitive performance for multiband and multimode smartphones, tablets and other IoT devices.”

Commenting on the IoT opportunity, YJ Kim, MagnaChip’s interim Chief Executive Officer, said, “We believe there is tremendous growth opportunity in the IoT market and our participation is part of our overall strategy to broaden our product portfolio in new markets. MagnaChip’s IoT task force and business consortium with key business partners will reinforce our position as a key manufacturing service provider in the expanding IoT market.”

ByGianni PRATA

28nm FD-SOI cryptocurrency ASIC first to debut in silicon, surpasses expectations with 0.45V operation

(Courtesy: SFARDS)

SFARDS’ SF3301 cryptocurrency ASIC is the world’s first chip to use 28nm FD-SOI. Surpassing expecttions, it operates at a stunning 0.45V. (Courtesy: SFARDS)

Right on schedule, the SFARDS cryptocurrency ASIC on 28nm FD-SOI has made its debut in silicon, and is surpassing expectations. In what is clearly a stunning success, the company announced that the ASIC’s lowest working voltage is 0.45V. This means it operates stably at a power supply voltage that’s about half that of competing 28nm offerings.

An article published on the SFARDS website (see the whole thing here) said, “Using the latest in FD-SOI processing technology, SFARDS has successfully completed its 28nm SF3301 dual-algorithm ASIC chip. The SF3301 is the world’s first chip to use this manufacturing process and is at the same time the world’s first 28nm dual-algorithm (SHA-256 & Scrypt) chip, capable of mining these two algorithms simultaneously or singularly.

“SFARDS’ SF3301 fully utilizes the advantages of the FD-SOI technology. This brings increased forward body bias; the chip is operational at lower voltage while maintaining a higher frequency. The chip boasts impressive power efficiency while affording high hash power, allowing for much lower wastage per hash. The ASIC’s lowest working voltage is 0.45V.”

As noted in ASN’s Buzz in March 2015 (read it here), cryptocurrency (the best-known example of which is Bitcoin) depends on “ledgers” supported by bitcoin “mining” chips.  As well-explained in an arstechnica piece (read it here), while some Bitcoin mining is done on CPUs and GPUs, serious mining requires much faster and lower power ASICs in the hardware.