ASN had a chance to talk to François Brunier of Soitec, who’s leading this important project.
Advanced Substrate News (ASN): Can you tell us briefly about OCEAN12?
Francois Brunier (FB): OCEAN12 stands for Opportunity to Carry European Autonomous driviNg further with FD-SOI technology up to the 12nm node.
It’s an ECSEL project (ECSEL is the Electronic Components and Systems for European leadership, an EU-driven, public-private partnership that funds innovation). The budget is 103M€ for a European consortium of 27 partners from 7 different countries. The topic is “Ultra-low power computing solutions for automotive and aeronautics using all the range of FD-SOI technologies”, and Soitec is the project leader.
ASN: Why is it needed?
FB: As of today a car has around 500 million transistors. These electronic components represent already an important vector of valorization and differentiation for the automotive industry and for the consumer. The increased autonomy of the vehicles will require a very strong build-up of computational capacities. 50 to 100 times more transistors could be required for a level 5 (fully autonomous car). Following this trend an autonomous car will require a power consumption equivalent to that of 50 to 100 computers running continuously (without taking into account the car propulsion).
The power consumption of these components becomes a key element in the choice of technologies. We believe that our technologies on SOI present the best assets to meet this challenge.
The FD-SOI solutions developed in OCEAN12 offer a palate of different solutions to this challenge. Indeed the solutions will come with components that are more performant for data processing (including Artificial Intelligence), much more energy efficient, more highly-integrated and smaller to fit in embedded systems like in autonomous cars, reliable, and enabling safe connectivity.
The OCEAN12 project will demonstrate that SOI technologies are able to meet these challenges through relevant demonstrators in the targeted fields.
ASN: What are the project goals?
FB: OCEAN12 will bring concrete solutions to the main challenges of smart connectivity and low power consumption for autonomous driving in the automotive industry.
As such, OCEAN12 will build awareness around the key enabling technologies in substrate development, transistor behavior, and the design and fabrication of components up to the system and end-user application levels. We will show that the technology is useful for automotive and aerospace applications, which are strategic sectors for Europe. Having the whole supply chain in Europe means having trusted and secured components made in Europe.
The OCEAN12 project goals stand on three pillars:
ASN: Can you tell us more about the demonstrators? When will we see them?
FB: There are four demonstrators. All these demonstrators will be delivered by the end of the project in 2021:
ASN: Can you tell us more about the partners?
FB: The OCEAN12 consortium of 27 partners involves 8 large groups, 9 SMEs and 10 universities/RTOs. These partners come from 7 different European countries.
The eight large groups include: Soitec, the world’s leading provider of FD-SOI substrates; EVG, a leading global equipment supplier; GlobalFoundries and STMicroelectronics, the two major European FD-SOI foundries; and Bosch, a Tier 1 automotive supplier. At the top of the value chain, high-end European automotive manufacturer Audi, the avionics industrial giant Airbus, and Thales for security issues, will develop product demonstrations.
Ten highest-level research institutes support the industrial consortium. They include CEA-Leti (FR), Fraunhofer (GE), IMS (FR), INP Grenoble (FR), TU Dresden (GE), U. Paderborn (GE), Bundeswehr U. Munich (GE), Eberhard Karls U. Tübingen (GE), Instituto de Telecomunicações (PT), and Warsaw UT (PL). They increase the competitiveness through technological innovation and transfer of technical know-how while gaining new expertise working with global leaders.
In addition, OCEAN 12 has a very strong SME consortium covering the supply chain in the fields of new equipment, IP, system integration and fabless companies. They include: IBS, UnitySC (HSEB), MunEDA, Kalray, AED Engineering, ISD, EVOTEL, M3 Systems and Design&Reuse.
All these partners have longstanding experience of cooperation in various national and international frameworks and are specialists in their field of activity. Their contributions are essential for the success of the project.
ASN: What is the timetable?
FB: The project started on April 1st 2018. The kick off with all the partners was held at Soitec on 29 September 2018. It was a great success. The project runs through December 2021, by which point everything has to be demonstrated.
ASN: Can you clarify the funding structure?
FB: The budget is about €103.6M. If the project succeeds, we get European Commission funding. In that case, just over 20% of the eligible cost – about €23M – is subsidized at the European level. The seven countries with companies or organizations participating in the project will then roughly match the European subsidies, contributing about €27M. However, the majority of the budget is paid by the participating companies and organizations.
These ECSEL-type public-private projects are a tried and true model in Europe, maximizing synergy across ecosystems. For example, we saw how well it worked with RF-SOI, which also had European and national funding, and is now in every smartphone made in the world.
To conclude, in the name of the consortium I’d like to thank the ECSEL JU, the European Commission and our National Funding Agencies from France (DGE), Germany, Portugal, Greece, Spain, Austria and Poland. Such a project would not exist without them.
The SOI Consortium and member companies had a significant presence at two important events in China recently: the World Semiconductor Congress (WCS) in Nanjing and the SOI Academy, including an FD-SOI Training Day in Shanghai.
Nanjing is especially known as a leading RF chip design hub in China, but WCS went well beyond RF. The three-day 2019 event was held at the Nanjing International Expo Center. It attracted over 30,000 visitors, 5000 of whom attended the various summit forums.
The SOI Consortium organized the SOI Forum, which was part of an afternoon Innovation Summit. Presentations were given by members of the SOI Consortium team, and by leaders from our membership, including Simgui, NXP, Incize, ST, IBM, Cadence and Xpeedic. Some of those presentations are now available from our website — click here to get them.
Earlier in the day, SOI Consortium member VeriSilicon participated in a morning session on AI and IoT Wireless Communications. They presented their low-power Bluetooth design platform for GlobalFoundries 22FDX, and CEO Wayne Dai moderated a lively round-table discussion.
Following hard on the heels of the Nanjing event, the SOI Consortium team and members headed to Shanghai for the SOI Academy 2019, hosted for the second year in a row by member SIMIT (Shanghai Institute of Microsystem and IT under the Chinese Academy of Sciences). The two-day event attracted more than 250 professionals from more than 100 domestic and foreign IC companies and research institutes.
Keynotes by SOI Consortium Executive Director Carlos Mazure, SITRI CEO Mark Ding and Jean-Eric Michallet, Head of the Microelectronics Components Department at Leti and bizdev director for the SOI Consortium focused on the SOI ecosystem. The SITRI and Leti talks also gave updates on their research and industrialization alliance. Further talks were given by leaders from Soitec, GlobalFoundries, VeriSilicon, IBM and Xpeedic. These addressed the growing FD-SOI ecosystem, applications in automotive electronics, 22 nm and 10 nm FD-SOI devices, advanced SOI substrate technology, China’s FD-SOI development, the FD-SOI manufacturing process, product design, EDA tools and all aspects of industry’s software and modeling value chain.
Several speakers noted that more and more local Chinese customers are actively adopting FD-SOI for low-power, high-performance chips.
The second day was devoted to hands-on professional training, given by experts from Leti using an actual PDK and punctuated by in-depth discussions. This helped the IC designers to fully understand the advantages and flexibility of FD-SOI in low-power logic, analog/mixed-signal and RF.
All in all, “It was a great success,” concluded Jean-Eric MICHALLET, Head of the Microelectronics Components Department at Leti and bizdev director for the SOI Consortium. Plans for the next SOI Academy are already underway, with plans to extend the topics to include more on photonics, RF, power and MEMS.
Why FD-SOI? What can you do with it that you couldn’t do before? That was the big question from IHS Markit’s Matthew Short that kicked off the first panel discussion at the SOI Consortium’s Silicon Valley Symposium. And there were some great answers.
Here in this final part of our coverage of the event, we’ll detail who said what in the two panel discussions, as well as the presentations by Leti, Intento Design & the SOI Consortium’s IP/EDA roundup.
If you missed the previous two installments of our coverage, you can catch up on the rest of the presentations in part 1 (NXP, Samsung & more) here and part 2 here (Synaptics, GlobalFoundries & more). Almost all of the presentations are now freely available under “events” on the consortium website – or just click here to get them.
The presentation by Matthew Short, Sr. Director of IoT Technology at IHS Markit, was not specific to SOI, but it sure did lay out out the market opportunities. Entitled IoT, 5G, ADAS and AI Market, it’s available on our website. Matt spent most of his career in chip design at NXP/Freescale, so he really has an engineer’s perspective on where this all is going. At IHS Markit, they define IoT as anything with an IP address. Over the past year more than 10 billion devices were shipped, and there were more “things” than cellular handsets, so the world has really changed. He outlined the growth drivers, suggested that 5G won’t be a “wow” thing for consumers, and noted there is a lot of debate raging regarding how smart sensors should be (the Tier 1’s want smart).
He was then joined on the stage by the participants in the first panel discussion, which looked at product and application drivers. That included: NXP Fellow Rob Cosaro; Tim Dry, Director of Edge & Endpoints Marketing at Samsung Foundry; ST biz dev director Roger Forchhammer; CoreAVI biz dev VP Lee Melatti; Nokia VP Michael Reiha; and Analog Bits EVP Mahesh Tirupattur.
First Short asked why customers wanted more integrated solutions. For CoreAvi, it’s about safety, for ST in automotive it’s about security, for Analog Bits, it’s about integrating more analog, for Nokia it’s just a necessity.
Then he asked Why FD-SOI? What can you do that you couldn’t do before? For ST, which is doing MCUs for automotive, it’s about energy efficiency, speed, the density of non-volatile memory and the robustness of the technology. For NXP, it’s back biasing, low voltage and power numbers never seen before. “FD-SOI really makes a difference in the products we can bring to market,” said Cosaro. For CoreAVI, it’s the long-term power impact. And for Analog Bits, “Customers see huge benefits,” said Tirupattur, for cost sensitive applications. He has customers selling their technology in high volumes in FD-SOI.
What about edge vs. cloud? For Nokia, it’s monolithic integration for best-in-class RF, advanced memory, biasing and voltage regulation adding a layer of intelligence. Samsung sees edge as distributed cloud, and CoreAVI sees safety in the edge, because you can’t completely rely on the cloud.
Where are the weak points in the FD-SOI ecosystem? For Samsung, more people need to use back biasing. “People need to use the knobs,” said Dry. For Analog Bits, the next step is innovation around back biasing, as many in logic don’t understand the benefits, so the ecosystem needs to promote the value proposition. ST suggests that with more products out there, customers will see the benefits. NXP did “a lot of the heavy lifting” at 28nm – now you need more people using these nodes, not just the cellphone nodes.
How will the architecture change? For NXP, it’s all about memory bandwidth. For Samsung, it’s the promise of analog and interconnect. Nokia sees the back-end and heterogeneous integration with FD-SOI and RF enablement. Analog Bits’ Tirupattur said he’s pushing his engineers for even lower power in a still smaller form factor, noting that most analog engineers had been more focused on performance than power, but now that’s changed. For ST, it’s AI/ML throughout automotive, and FD-SOI is beneficial there.
Research giant Leti’s presentation was entitled Applications Around the Connected Car. 85% of Leti’s €315M budget comes from R&D contracts with its 350 industrial partners. Truly a driving force in FD-SOI, Leti is involved in a dizzying array of projects. For the connected car, they cover (much of it on SOI): high precision & smart sensing, embedded processing & fusion, new computing paradigms and deep learning, ultra-low power computing nodes & framework, ultra-low power connectivity for IoT, energy management and scavenging, and security. They do vision at the edge, 3D technology for smart imagers, and ways to dramatically reduce power. They’ve got a Qbits platform on FD-SOI for AI at the edge, a super low power neural network accelerator, and ULP connectivity. Check out the presentation for lots of details.
SOI Consortium Executive Co-Director Jon Cheek gave a quick round-up presentation aggregating various IP and EDA offerings entitled , SOI EDA/IP Overview. It is taken from recent member presentations including Cadence, Silvaco, VeriSilicon, Synopsys and GlobalFoundries, giving you an idea of how dynamic the ecosystem has become.
While the logic side of the design equation has long had robust automation tools, some consider the analog side as sort of black magic. New consortium member Intento Design aims to fix that. Here at ASN we covered their work with ST briefly a few months ago here. At the SOI Symposium, the company’s CEO Dr. Ramy ISKANDER presented their solution in ID-XploreTM: A Disruptive EDA for Emerging FDSOI Applications. Intento, a partner in GlobalFoundries FDXcelerator program, has cognitive software for first-time right analog design. It determines the appropriate static and dynamic body biasing ranges to meet PVTB (Process/Voltage/Temperature/Body Bias), and is fully integrated into the Cadence Environment. They produced multiple correct-by-construction FD-SOI designs, and the total time spent to generate eight candidates FD-SOI designs took less than a day.
The last panel discussion, entitled Are the Tools in the Box? was moderated by the Consortium’s Jon Cheek. Participants included: VeriSilicon SVP David Jarmon; Arm PDG Marketing VP Kelvin Low; NXP’s Stefano Pietri, Technical Director of the company’s Microcontrollers Analog Design Team; Jamie Schaeffer, who’s GF’s Sr. Product Offering Manager for 22FDX and 12FDX; and Cadence Strategic Alliances Director Jonathan Smith.
Yes, the tools are in the box. Smith of Cadence said they’re providing them, and NXP’s Pietro said that they’re very well positioned in his specialty, analog. VeriSilicon has IP, and anything they don’t have in house they’ll license.
So why be afraid of body biasing? NXP has proof by example – they see such huge cost advantages that they try to leverage it as much as possible. GF’s doing training, since each area (automotive, IoT, etc.) has different needs. Some VeriSilicon customers already see such substantial benefits from FD-SOI that they’re not bothering to do biasing. Cadence points out that the Arm POP announcement is huge, and Arm’s Low wondered if the SOI Consortium could do an IP portal? “Our sales departments need to explain the advantages to our customers!” said NXP’s Pietro.
From the audience, NXP VP & longtime FD-SOI proponent Ron Martino (who, btw, wrote some great articles for ASN when they first got into FD-SOI – read them here), asked why designers think FD-SOI means a lot of corners? How do we convince the industry that FD-SOI simplifies design? Cadence is working with GF, responded Smith, and will have some big new at Arm’s TechCon this fall. “We need more training and marketing to show it’s not scary,” he added. For GF, the corners don’t get more complicated, and they’re working with Dolphin Integration on getting them covered early in the planning. Ease of access to IP will help, per Arm.
And in a great concluding remark, VeriSilicon’s Jarmon said, “The craft is being automated. The more we work together, the greater success of FD-SOI.”
Join us! In partnership with our members, the SOI Consortium is co-organizing and participating in two key SOI events coming up in China over the next few weeks. On May 18th, we’ve put together an SOI Forum at the World Semiconductor Congress (WCS) in Nanjing. And on May 23rd & 24th, we’ve teamed up with our members SIMIT, Sitri and Leti for another in our series of SOI Academies, including an FD-SOI Training Day. (The last one this past winter was a terrific success – read about that here if you missed our coverage at the time.)
At WCS, the SOI Forum (sub-forum #8) is part of the afternoon Innovation Summit. We’ll cover the broader SOI ecosystem, including both RF-SOI and FD-SOI – from wafers to design through manufacturing. Presentations will be given by members of the SOI Consortium team, and by leaders from our membership, including Simgui, NXP, Incize, ST, IBM, Cadence and Xpeedic. Click here or scan the QR code for the full program and registration information.
Also at WCS, SOI Consortium member VeriSilicon will be participating in a morning session on AI and IoT Wireless Communications (sub-forum #4). They’ll be giving a presentation on their low-power Bluetooth design platform for GlobalFoundries 22FDX, and their CEO Wayne Dai will be moderating a round-table discussion. You can get more information on that (in Chinese only, tho) here, or follow VeriSilicon on WeChat.
The SOI Academy in Shanghai is an opportunity for experienced designers to gain solid expertise in FD-SOI. The event begins in the afternoon of May 23rd with a series of informative plenary talks by members of the SOI Consortium team, and by experts from our members Leti, Soitec, VeriSilicon, GlobalFoundries and NXP. The FD-SOI Training starts the next morning, on May 24th.. This is a hands-on event lead by top experts from Leti. The morning is devoted to digital design in FD-SOI, and the afternoon to RF design (including for 5G) in FD-SOI. Attendees will get a comprehensive understanding of design techniques for low-power chips leveraging the multiple benefits and flexibility of FD-SOI technology. Get more information here, or from the WeChat QR code.
We’ve got a busy schedule! To keep up to date with where we and our members will be promoting the SOI ecosystem, be sure to check our Events page regularly.
Key takeaway #2: If you need a Goldilocks process node – where you’ll get just the right balance between active power, unit cost and investment – look to FD-SOI. And, btw, the IP landscape has improved dramatically. Those were just some of the great points made by Huibert Verhoeven (shown above), GM/SVP of Synaptics’ IoT Division in his talk at the recent SOI Symposium in Silicon Valley.
BTW, if you missed part 1 of our coverage —Silicon Valley SOI Symposium a Huge Success. Key Takeaways (Part 1) Here. – you’ll want to be sure to read it, too. Almost all of the presentations are now posted on our website – click here to access them.
In this post here, we’ll cover presentations by Synaptics, GlobalFoundries, STMicroelectronics, Anokiwave and Dolphin Integration. It was a really full, day, so be sure to stay turned for Part 3 of our coverage to follow shortly: it will highlight the remaining presentations and panel discussions.
Synaptics’ Verhoeven’s presentation Revolutionizing User Experience Through Secure Neural Network Acceleration at the Edge was about Smart Home and using SOI. Synaptics is a human interface (HMI) company that’s been doing neural networks since 1986. They’ve always been on the leading edge, from their first shipment of PC touchpads to becoming a dominant force in all things HMI today: they now ship over a billion units annually.
They currently have SOI products shipping with dedicated neural networks for voice, he said. European [privacy] regulations have played a part in driving their use of SOI, as have challenges regarding power and heat. Things are getting smarter at the edge. For example, not only do users want their coffee machine to offer the usual morning espresso, Synaptics says that the next step is for your coffee machine to recognize you’re looking extra tired and ask if you might want a double?!
For them Smart Home and multi-modal applications are the primary area of interest, as well as some automotive. Although their biggest customers have resources, others need guidance. Voice is a critical component, but now you also need video and display.
Why SOI? Their HMI vision requires low power, significant computation and dedicated neural network hardware, explained Verhoeven, so FD-SOI with RF meets their needs. “22nm SOI is a Goldilocks IoT Process Node,” he proclaimed. It gets the combination of active power, unit cost and investment just right. What’s more, he said, “The IP landscape has improved dramatically. Our choice of SOI was not an accident.” Be on the lookout for more products leveraging FD-SOI over the next six months, he concluded.
At this point on SOI, they’ve got 1 TOPS products with dedicated NPU for speakers, soundbars, Wi-Fi mesh, appliances, STBs and smart displays. These products have voice and sensor real-time (RT) AI. Next up is >4 TOPS on SOI with dedicated NPU, targeting STBs and smart displays with voice, video, imaging and RT AI.
“Our clients are at the forefront of changing the world,” declared Mark Granger, VP of the Automotive Product Line at GlobalFoundries. His presentation, Capturing High Growth Market Opportunities with SOI, detailed how mobility, automotive and IoT are the growth markets for SOI. So not unsurprisingly, GF’s 22nm FD-SOI technology, 22FDX, is seeing particular traction in mobile, edge, wearables and automotive.
They’ve got twice as many tape-outs this year as they did a year ago, he noted. GF’s SOI portfolio includes 22FDX®, 45RFSOI and 8SW/7SW RF SOI for 5G/mobility; 22FDX for automotive (fully qualified for automotive Grade 2, with Grade 1 on the way); and 22FDX, 130RFSOI and 8SW/7SW RF SOI for IoT.
GF has announced a stream of good news recently:
You might have heard about the Dolphin Integration news, as we covered it recently here at ASN (if not, be sure to read it here). Dolphin’s IP and methodology solutions address energy efficiency challenges. Automated transistor body biasing adjustment can achieve up to 7x energy efficiency with power supply as low as 0.4V on 22FDX designs. At the Silicon Valley event, Dolphin Integration CEO Philippe Berger provided additional information in his talk, FD-SOI IP Platform for Energy-Efficient IoT SoC.
In another GF-related talk, Nitin Jain, the CTO of longtime GF RF-SOI customer Anokiwave presented Unleashing the mmWave Phase Array Using SOI for 5G & Satcom. Anokiwave is a fabless semi IC company (you’ll find a good technical discussion of mmWave phase array written by their Chief Architect here). They do active antennas (aka phased array), something the military’s done for a long time, but now Anokiwave is bringing it to new markets and applications including radar, satcom and 5G. What they’ve been able to do is planarize the active antennas. They use GF’s 45RFSOI process technology for phased array systems because of the cost, performance, scalability and system enhancements it enables. 45RFSOI, he explained, is ideal for beam-forming FEMs (including the switches, LNAs and PAs). The move to 5G/mmWave is going to require a lot of antennas, so these Anokiwave ICs are headed to high volumes, concluded Jain.
As Roger Forchhammer, Director of Business Development at STMicroelectronics pointed out in his presentation, Automotive FD-SOI Microcontrollers with Embedded PCM, ST pioneered FD-SOI (and that was almost a decade ago, btw). Then in February 2019, they announced a world first: they’d begun sampling 28nm FD-SOI microcontrollers (MCUs) with embedded non-volatile memory (eNVM) based on embedded Phase-Change Memory (ePCM) to 10 alpha customers. These MCUs target powertrain systems, advanced and secure gateways, safety/ADAS applications, and vehicle electrification.
(In case you want technical details, the breakthrough ePCM eNVM was first presented at IEDM in December 2018 – you can get the presentation that accompanied the paper, Truly Innovative 28nm FDSOI Technology for Automotive Microcontroller Applications embedding 16MB Phase Change Memory, from the ST website.)
In his Silicon Valley presentation, Forchhammer said they’re now doing Stellar, a whole family of automotive products on FD-SOI. To do it, they’d taken an existing device and moved it to 28nm FD-SOI with ePCM, which they manufacture at their fab in Crolles, France. A major advantage for automotive he cites is that in software updates it’s bit-level programmable. “ST is fully behind FD-SOI,” he concluded, adding that we’re see more automotive as well as IoT products coming soon.
Well folks, that’s all for this post. We’ll finish up our coverage of the SOI Consortium’s 2019 Silicon Valley Symposium in the next ASN post (there was so much to cover!). So please stay tuned.
Takeaway #1: As NXP VP Ron Martino noted in his opening keynote at the recent SOI Symposium in San Jose, FD-SOI is the technology platform for enabling edge computing, and ultra-low power is the sweet spot.
Organized by the SOI Consortium with support from our members, the recent SOI Symposium in Silicon Valley was an enormous success. Close to 300 decision makers signed up – more than double what we saw just a couple years ago. Attendees spanned the ecosystem: from end-users to design to foundries and right up to the investment community. The presentations and panel discussions were absolutely terrific, and almost all are now freely available – click here to get them.
The focus was heavily on FD-SOI this time, but some very interesting RF-SOI talks were given as well. This was a day packed with presentations by players from across the SOI ecosystem. In this post, we’ll only cover a few. But the others will follow quickly, so watch this page. And now without further ado, let’s dive in.
NXP is designing FD-SOI into many new products, said Martino, GM of the i.MX Processor Application Product Line. There’s a new wave of products – generically you could call them IoT but in fact they’re found throughout the industry. It’s about interacting with the cloud, so edge processing is critical. His presentation, Embedded Processors for Future Applications, is now freely available for downloading from our website.
The new i.MX7ULP is a great example of ULP in the sweet spot. From a design standpoint, it leverages IP, power optimization, and what he described as “starter biasing”. That gets them the long battery life with 2D & 3D graphics they need for wearables and portables in consumer and industrial applications.
Having deepened their expertise in biasing, NXP has now moved on to “advanced biasing” for the next generation of products. For example, the i.MX RT ULP (real-time, ultra-low-power) series are “cross-over” processors, which Martino says are the “new normal”. They deal with a high number of sensor inputs. The i.MX RT 1100 MCUs, which have been qualified for automotive and industrial applications, are breaking the gigahertz performance barrier with a low-power, 28nm FD-SOI process.
Another new product leveraging advanced biasing is the i.MX RT 600. They’ve done hardware acceleration on specific functions and optimized around visionand voice integration at low cost and power.
Likewise for the i.MX 8 and 8X subsystems for automotive and industrial applications. At Embedded World, they showed it driving advanced OLED screens, cameras (for parking, for example), V2X, audio, user monitoring (like driver pupil tracking), and integration into the windshield in a heads-up system. This is the high end of the capability of 28nm FD-SOI, he said. It’s a 6 CPU core system with multiple operating systems, about which he said: “It’s the dashboard…it’s amazing.”
FD-SOI enables a scalable solution for real-time and general compute with the lowest leakage memory, the best dynamic and static power, Martino concluded. NXP’s leadership in body biasing is enabling edge compute, and we can expect to see more content coming soon.
In another NXP presentation later in the day, Stefano Pietri, Technical Director of the company’s Microcontrollers Analog Design Team caught a lot of people’s attention. A wave of cameras went up to capture each of his slides in Analog Techniques for Low Power, High Performance MPU in FD-SOI – but you can get the whole thing now from our website. It’s a very technical presentation, in which he details the many ways FD-SOI makes the analog team’s job easier, enabling them to get performance not available from bulk technologies. They developed a lot of in-house expertise and IP (see slide 16 for a catalog of the IP).
Tim Dry, Director of Foundry Marketing: Edge and End Point presented Samsung’s FDS with MRAM: Enabling Today’s Innovative Low Power Endpoint Products. In a telling first, Samsung has made this presentation available on our website.
FD-SOI covers the wide range of requirements for intelligent IoT, he explained: from high to low processing loads; and active to dormant processing duty cycles. That includes chips that will last for ten years, and need to be able to wake up fast and kick right into high performance. These products are 50% analog, and packaging is part of the solution (especially for the RF component).
Samsung has been shipping 28nm FD-SOI (which they call 28FDS) since 2015, first in IoT/wearables, then in automotive/industrial and consumer. Yields are fully mature. In March 2019, they announced mass production of eMRAM on 28FDS. It’s a BEOL process, adding only 3 masks. It cuts chip-level power by 65% and RF power by 76% over 40nm bulk with external memory. Beyond the fact that it’s 1000x faster than eFlash, eMRAM also has other advantages that make it especially good for over-the-air updates, for example.
Samsung also has RF and 5G mmWave products shipping in 28FDS. The company has a fantastic ecosystem of partners helping here, said Dry. In AI at the endpoint, they’re shipping IoT products for video surveillance cameras: some are high speed, but some are also low speed – it depends on the detection use case. And most importantly for the design ecosystem, the IP is all ready.
Next up for Samsung is 18FDS, which will ship this year with RF, then in 2020 with eMRAM. 18FDS, Dry said, is optimized for power reduction. Compared to 28FDS, it’s got 55% lower power consumption, 25% less area and 17% better performance at the same power. You’ll hear more about it as well as their design services if you’re at the Samsung Foundry Forum in May (registration info here).
Kelvin Low, VP of Marketing for Arm’s Physical Design Group (PDG) gave a presentation entitled Biased Views on the Industry’s Broadest FDSOI Physical IP Solution. By way of background, Arm and Samsung Foundry recently announced a comprehensive, foundry-sponsored physical IP platform, including an eMRAM compiler for 18FDS. In case you missed it, at the time Arm Senior Product Marketing Manager Umang Doshi described the offering in an Arm Community / Developer physical IP blog, which Arm graciously agreed to share with ASN readers.
At the SOI Symposium, Low emphasized to the audience that Arm now has the broadest range of FD-SOI + IP solutions. It addresses mobile, consumer, IoT, automotive and AI/ML.
There are 18FDS POP (processor optimized pipe) packages for Arm Cortex-A55, Cortex-R52 and Cortex-M33 processors. IP integrates biasing and a number of standard PVTs (corners). And since the Samsung platform is foundry-sponsored, it’s free.
Arm did a test chip with eMRAM, which they’ve just gotten back. It’s functional (some details are available in slide 14 of their presentation), and the company is now preparing a demo board that they’ll be showing shortly. Watch this page!
That’s all for this post. The next post — part 2, covering presentations by Synaptics, GlobalFoundries, STMicroelectronics, Dolphin Integration and Anokiwave — is now available. Click here to read on.
FD-SOI for RF and mmWave communications is a hot topic. In high-data rate communications like RF and millimeter-wave devices in particular, FD-SOI delivers high-performance with numerous unique advantages, making it most likely the fastest RF-CMOS technology on the market.
If you’d like to take a deep dive and learn more about it, Soitec and Incize are sponsoring a free, full-day workshop in Grenoble on April 4th, 2019. Click here for registration information. The workshop follows the day after the IEEE/EDS EuroSOI-ULIS conference there (you can read about the full conference in a previous ASN post).
This technical workshop will cover the FD-SOI technology platform with a focus on its compatibility with RF & mmWave communications. Attendees will hear from notable FD-SOI leaders and experts from leading industry and research institutions presenting updates on key developments and building blocks across the semiconductor value chain. Topics will include circuit design, device fundamentals, simulation and characterization of RF devices, test, CMOS technology and substrate technologies enabling FD-SOI. In addition, the workshop will include an overview about how FD-SOI technology is benefiting current and future end user applications.
Here’s the agenda:
STMicroelectronics is now sampling 28nm FD-SOI microcontrollers (MCUs) with embedded non-volatile memory (eNVM) based on ePCM to alpha customers. Field trials meeting the requirements of automotive applications and full technology qualification are expected in 2020. These MCUs—the world’s first to use ePCM, which stands for embedded Phase-Change Memory—will target powertrain systems, advanced and secure gateways, safety/ADAS applications, and Vehicle Electrification. (Read the full press release here.)
“Having applied ST’s process, design, technology, and application expertise to ePCM, we’ve developed an innovative recipe that makes ST the very first to combine this non-volatile memory with 28nm FD-SOI for high-performance, low-power automotive microcontrollers,” said Marco Monti, President Automotive and Discrete Group, STMicroelectronics. “With samples already in some lead-customers’ hands, we’re confirming the outstanding temperature performance of ePCM and its ability to meet all automotive standards, further assuring our confidence in its market adoption and success.”
ePCM presents a solution to chip- and system-level challenges, meeting automotive MCU requirements for AEC-Q100 Grade 0, operating at temperature up to +165°C. In addition, ST says its technology assures firmware/data retention through high-temperature soldering reflow processes and immunity to radiation, for additional data safety.
Architecture and performance benchmark updates were presented the most recent IEDM (December 2018 in San Francisco) in a paper entitled Truly Innovative 28nm FDSOI Technology for Automotive Micro-Controller Applications embedding 16MB Phase Change Memory (F. Arnaud et al). As of this writing, the IEDM 2018 papers are not yet posted on the IEEE Xplore Digital Library site. However, the ppt that ST presented at the conference is available here.
For more in-depth information on ePCM, see the ST PCM page. To learn more about how it compares with competing technologies such as eMRAM, read Embedded Phase-Change Memory Emerges by Mark Lapedus of SemiEngineering. Papers describing other eNVM solutions on FD-SOI were also presented at IEDM 2018. Samsung’s is entitled Demonstration of Highly Manufacturable STT-MRAM Embedded in 28nm Logic (Y. J. Song et al). GlobalFoundries’ is entitled 22-nm FD-SOI Embedded MRAM Technology for Low-Power Automotive-Grade-1 MCU Applications (K. Lee et al).
It should be a good year across the SOI ecosystem, with new products, players, IP, technologies and tools — and high volumes.
What’s new? Let’s start with the people, as the Consortium welcomes new team members. Jon Cheek of NXP will join Carlos Mazure as Executive Co-Director. He’ll be replacing ST’s Giorgio Cesana in that role – and goodness knows those are some big shoes to fill. Giorgio has given of his time and expertise so tirelessly over many years. He’ll of course still be a key resource for the SOI ecosystem, and though we’ll miss him here at the Consortium, we know he’ll be doing great things in SOI at ST. So a heartfelt thanks to Giorgio Cesana from all of us.
Jon Cheek has a long history in engineering management at companies that have been leading users of SOI: AMD, Freescale and now NXP. As such, he understands what companies need to design great products, and how the Consortium can help further build, promote, connect and support the ecosystem. The Consortium team also welcomes Jean-Eric Michallet of Leti, who’ll bring deep bizdev expertise and a keen sense of what it takes to reach further into the ecosystem. (Astute long-time ASN readers might remember his post from five years ago about 3D monolithic integration – now dubbed “Cool Cube” by Leti.) And finally, look to hear more from and about the Consortium, as our team is rounded out with the addition of the comm & marketing savvy of Erin Berard of Soitec.
In addition to new team members, the Consortium is very pleased to welcome new member Applied Materials. Though new to the Consortium, AMAT has a long history in the heart of SOI ecosystem – in fact they’ve been working with SOI wafer-leader Soitec for over 25 years. AMAT ion implanters are a key enabler to what became and is Soitec’s industry-leading Smart CutTM SOI wafer manufacturing process. And of course AMAT equipment is used to make virtually every chip in the world, so their breadth of vision as a consortium member is clearly a fabulous addition.
2019 will also be marked by the expansion of the highly successful SOI Academy series, the first of which was held this past fall in Shanghai. We’ll keep you posted as these and other Consortium events are announced throughout the year. In fact, 2019 marks a decade of (excellent!) SOI Consortium events events around the world: our first symposium was held back in 2009. Kicking off this year, save April 9th on your calendar for our Annual SOI Silicon Valley Symposium. Then watch this page for more events across the globe.
What will the year bring? On the product side, RF-SOI for 5G is of course super hot. Last summer, a SemiconductorEngineering headline proclaimed RF-SOI Wars Begin. And what we heard at the International RF-SOI Workshop last fall in Shanghai (presentations here) certainly confirmed that in the coming year the race will continue unabated.
And for FD-SOI, you might want to read the SE series published over the last six months. The latest, published a couple of weeks ago looks at FD-SOI at the Edge. There are some great insights from SOI Consortium members there. In terms of products, too, there’s lots of activity.
Last summer, Samsung indicated they’d taped out over 60 products since they first began offering 28FDS three years ago. It’s a trend they see accelerating. Full production of 18FDS is slated for this fall.
And also last summer GlobalFoundries indicated they had over 50 client designs on 22FDX. “We’re only just beginning,” said GF CEO Tom Caulfield at the time. “We have found a way to separate ourselves from the pack by emphasizing our differentiated FD-SOI roadmap and client-focused offerings that are poised to enable connected intelligence. ”
For its part, ST, as we learned at the last SOI Consortium Japan Workshop, has been doing FD-SOI for five years now. And while we don’t have number, we learned that some of those products are now in their second and third generations, and that some big FD-SOI chips coming out this year with embedded memory and RF, with especially good traction in mmWave, automotive and IoT.
So while the outlook for the overall industry is anyone’s guess for the coming year, the outlook for chips built on SOI technologies is very good indeed.
Lots of great information came out of the two days of workshops in Japan recently organized by the SOI Consortium. Some of the presentations are now posted on the consortium website (get them here).
The first day (held in Yokohama and sponsored by Silvaco) focused on FD-SOI and RF-SOI design. The second day (held at U. Tokyo) focused on More than Moore (especially silicon photonics, MEMS & sensors), and the SOI manufacturing ecosystem.
The 1st day panel discussion was so interesting we’ll give it a post of its own, then follow up with round-ups of the presentations from both days.
The morning panel discussion on end-user deployment for FD and RF-SOI was moderated by SOI Consortium Executive Director Giorgio Cesana. GF’s CTO Subi Kengeri led off saying that that 2017 had been the year of FD-SOI adoption. Samsung Director Adam Lee noted that in the beginning nobody believed it would get traction, but now everybody does, and Samsung is commercializing it: chips coming out this year will ramp in volume in 2019.
VeriSilicon CEO Wayne Dai said he sees great potential in IoT, where the volumes are high but fragmented. In IoT, he said, you need RF, but you really only need very high performance about 20% of the time, which is a perfect fit for FD-SOI.
ST Director John Carey noted that ST’s been using FD-SOI since 2014. They’ve fabbed products for cryptocurrency and infrastructure. Now in their second and third generations of designing with it, they’ve got some big FD-SOI chips coming out next year with embedded memory and RF. He sees it being particularly successful in mmWave, automotive and IoT.
The conversation then shifted to RF-SOI. Mostofa Emam, CEO of Incize, explained that since RF-SOI is already in every smart phone, it’s in a different situation from FD-SOI. The emphasis here is now on adding more blocks. “RF is an art,” he said. “It takes an artist. You need talented artists and tools.” One of the biggest challenges for fabs that are newcomers is models – not just at the transistor level, but also at the substrate level. The big players have addressed this, but Incize is working to support more foundries with new, innovative approaches, and helping them develop robust PDKs. The industry needs more good RF designers as well as better RF design flow, he concluded.
Coming back to FD-SOI, Cesana asked about non-volatile memory (NVM). Samsung’s Lee said they’ve already got NVM options including eMRAM for 28nm, and customers are now requesting eMRAM PDKs for the next node (18FDS). ST’s Kengeri added eNVM is important for FD-SOI, especially since flash is not scaling. While there are lots of options, MRAM gives you all the value, and in FD-SOI it only adds three more mask steps, so cost savings are maintained.
With respect to local computing for AI with FD-SOI, everyone agreed on the importance of the edge. In addition to RF, FD-SOI gives you density even at 28nm, explained Carey. You can manually control power with back biasing, so you get something very flexible, especially for NB-IoT applications where the battery will have to last for 10 years. In fact Kengeri sees FD-SOI as enabling fog/edge computing.
The next question was about 5G: which applications would we be seeing first, and how does FD-SOI help? Lee said Samsung’s seeing it for apps up to 10GHz as well as mmWave. Customers are telling them they want FD-SOI for technical reasons.
Kengeri expanded on that point, saying it comes down to fundamental physics: gate resistance, capacitance, mismatch. FD-SOI has lower Vmin and better Fmax compared to FinFETs, and that’s what tier-one players want.
Carey brought it back to RF-SOI (noting that ST’s introducing a 45nm version), which supports a large number of elements and increased complexity with smaller power budgets. Emam then asked the foundry guys about mmWave. Substrates won’t be the bottleneck he said, so what’s the FD-SOI/mmWave roadmap? Kengeri responded that GF’s ready. Lee said Samsung is also ready, and you’d see it next year on handsets. Samsung has engaged with customers on 30GHz for the middle of next year, he added: it’s qualified. Carey said ST sees it first in consumer premises equipment that’s connected by satellite.
Cesana then asked about image sensor processors (ISPs), noting that analyst Handel Jones has said this is a big opportunity for FD-SOI. You can do 3D integration with sensors, but heat makes noise, so you need technology that decreases heat production and doesn’t give you hotspots (which would be visible in the image). Kengeri pointed to challenges in power density, thermal envelopes and the RTS (random telegraph noise signal). Although there are a lot of options, FD-SOI plays well for thermals and noise, so GF sees a good opportunity here. Dai added that the industry needs volume applications for FD-SOI, and ISPs need to bring more logic closer to the camera. And he concurred that you need FD-SOI for the thermals: it’s very important.
In closing, Dai noted that as a design house, “We walk on two legs: FinFETs and FD-SOI.” 28, 22, 18 and 12nm FD-SOI all enable differentiation. In particular, you need something between 20nm and 7nm: FD-SOI is here. Asked about Japan in particular, Dai said beyond automotive he saw lots of potential in ULP for AVR. Kengeri added that for any applications besides performance-at-any-cost, FD-SOI is the right enabler.