Silicon Valley FD-SOI 2018 Training Day is April 27th – Don’t Miss It!

Following the immense success of last year‘s FD-SOI training day in Silicon Valley, the SOI Consortium has another one planned for the end of April this year. If you want to start learning how to leverage FD-SOI in your chip designs, this is a great place to start. Click here for information on how to […]

Chenming Hu: SOI Can Empower New Transistors to 10nm and beyond

FinFET and FD-SOI transistors look different but share a common principal that allows MOSFETs to be scalable to 10nm gate length. The good, old MOSFET is nearing its limits. Scaling issues and dopant-induced variations are leading to high leakage (Ioff) and supply voltage (Vdd),  resulting in excessive  power consumption and design costs. While these challenges […]

Important News Comes Out of Recent FD-SOI Workshop

The SOI Consortium’s 6th FD-SOI workshop, held just after ISSCC, yielded some exciting news. Most of the presentations are freely available for downloading from the SOI Consortium website. Here are the highlights. STMicroelectronics In a terrific presentation by Giorgio Cesana, Marketing Director at STMicroelectronics, he revealed that the company would be releasing a major product […]

SOI Luminaries Shine in IEDM Awards

Of those receiving top awards at the IEDM last month, over half (!) are stars of the SOI community. Wow. I discovered this while putting together the new listing of SOI-based papers at IEDM (don’t miss the summaries & links now posted in ASN’s most recent PaperLinks). At the IEDM, the IEEE also awarded the […]

The right choice for 22nm SRAM

What is the best transistor structure to meet SRAM performance and yield requirements at the 22nm node? The semiconductor device research group at UC Berkeley pioneered the FinFET structure in 1998. Now SOI-based FinFETs lead the field of candidate structures to eventually replace the planar bulk MOSFET. In the near term, yield and manufacturability may […]

Through the Back Gate

Might the Back-Gated FD-SOI MOSFET be the ultimate transistor structure? The fully depleted silicon-on-insulator (FD-SOI) MOSFET structure has been proposed for scaling CMOS technology to sub-45nm nodes. This is because short-channel effects (manifested in increasing off-state leakage with increasing drain bias and with decreasing gate length) are well suppressed in a FD-SOI MOSFET when the […]