Tag Archive wafers

Impressive! Soitec FD-SOI Press Conference in China = >150 Articles

FD-SOI makes sense for China. That was the key message SOI wafer leader Soitec made in a press conference on FD-SOI for a select group of journalists just before Semicon China this spring. News then quickly spread, and resulted in over 150 FD-SOI articles in the top China technology and business press.

Soitec also put together a super FD-SOI resource page, with lots of information in Chinese (you can see it here).

Soitec execs Thomas Piliszczuk, SVP of Marketing & Biz Dev and Christophe Maleville, SVP of the Digital Electronics BU joined forces with the CEO of the Chinese wafer company Simgui and the VP of the National Silicon Industry Group (NSIG). They made the case that FinFETs, bulk and FD-SOI will co-exist, FD-SOI is an excellent technology for China on two fronts:

  • for designers: who can create high-performance, low-power chips that can be manufactured for half the cost of FinFETs
  • for foundries: China fabs can take a bigger share of worldwide markets faster than they could with FinFETs
FDSOIecosystem

At its Semicon China ’16 press conference, Soitec highlighted the growing FD-SOI ecosystem (Courtesy: Soitec)

It was a powerful set of messages and clearly resonated throughout the press. Here’s a quick look (with a little help from Google Translate…) at what some of the top publications had to say.

ChinaByte

The ChinaByte article was one of many that reported on the key points that the Soitec folks made at their press conference, leading with the headline that FD-SOI can help the China innovation blueprint. Other points included:

  • fabs in China will use all the leading technologies, including FinFETs, but FD-SOI will provide a competitive edge for time-to-market and cost
  • FD-SOI is the best choice for chips that demand both high performance and energy efficiency
  • the ecosystem is growing fast, and Soitec is joining hands with companies in China to establish a strong local ecosystem
  • the FD-SOI wafer suppliers have achieved high-yield mass production

 CCINET

With a daily page views of over 1.7 million, CCINET is an influential site. The headline they ran was about how Soitec has promoted the ecosystem of FD-SOI and shares its innovate engineered substrates in China (link here). The thrust was that FD-SOI represents an opportunity for China. It covered the basics of FD-SOI, Soitec’s role as the leading global engineered substrate expert and partnerships in China with Simgui and Sitri, and FD-SOI’s strong ecosystem.

EETimes-China

EETimesChinaFDSOIimage001

(Courtesy: EETimes-China)

In a long and detailed piece, EETimes-China documented Soitec’s decade-long history in China, explained the special role of Soitec’s Smart CutTM technology in manufacturing the ultra-thin wafers for FD-SOI, then covered the scope of the ecosystem and the value propositions. There was also a follow-up piece by International Editor Junko Yoshida in the global edition of EETimes (see here).

And more!

Many publications focused on how Soitec and FD-SOI supports China’s innovation plan. They include: Power System Design; ECCN; Electronic Products China; 21ic; Electronic Engineering & Product World; EC.HC360; Microwave Journal; and China Electronic Market

EEFocusSoitecFDSOI

(Courtesy: EEFocus)

China Electronic News noted how FD-SOI supports “Made in China 2025”. The headline of the China Business Journal article (which got a lot of WeChat attention) positioned FD-SOI as a new choice for the semiconductor industry, and a chance for China become an industry leader. EEWorld cited Simgui’s and NSIG’s affirmation that FD-SOI adoption is moving fast and will have a bright future in China. EEFocus looked at how FD-SOI compares with FinFETs (very well!), and cites Soitec’s Maleville as saying FD-SOI represents a 6 million wafer/year opportunity in China by 2020.

SST/China called FD-SOI the best choice for mobile and IoT. Of course we can’t cover all the other articles here, but with the Soitec press conference having generated over 150 pieces in the China tech and biz press, that message is now clearly out there.

 

RF-SOI – Foundries Weigh In On New 300mm Wafers for 4G/LTE-A, 5G and IoT. Plus a Look at the Innovation Pipeline – Part 2 of 2

As you may have read in the first part of this series, Soitec (the industry’s leading supplier of SOI wafers) says its 200mm RF-SOI wafers have been used to produce over 20 billion chips, and the company is now in high-volume manufacturing of a 300mm version of its wildly successful RFeSI line (see press release here).

So far it’s been all about RF front-end module – aka FEM – chips that handle the back-and-forth of signals between the transceiver and the antenna, originally in 2G and 3G phones. For 4G/LTE-A (and 5G when that hits), there were new wafer innovations – and now 300mm wafers.

The newest RF-SOI wafers, Soitec’s RFeSI90 series (available in both 200mm and 300mm diameters), offer higher levels of performance such as better uniformity, which chip designers need to achieve greater control of transistor matching in analog designs. Plus with the new wafers designers can use thinner transistors and additional process options to improve RonCoff performance, the figure of merit that’s used to rate the performance of an RF switch. For Soitec customers (and really, anyone doing FEMs these days is a customer), all these advances plus the large supply of 200mm and 300mm wafers means that they can expand their production capacities for RF-SOI devices and produce more highly integrated ICs.

GlobalFoundries, for example, sang the praises of 300mm wafers for RF-SOI at a recent SOI Consortium forum in Tokyo. Here’s a slide from Peter Rabbeni’s talk, (he’s GloFo’s Sr. Director RF Product Marketing and Biz Dev), RFSOI: Defining the RF-Digital Boundary for 5G (you can get the full presentation here):

GloFo_RFSOI_300mm_Tokyo2016_slide24

Courtesy: SOI Consortium and GlobalFoundries

As you see in the slide above, RF-SOI champion Peregrine Semiconductor introduced the industry’s first 300mm RF-SOI technology – that was back in July 2015. Dubbed UltraCMOS® 11, it’s built on GlobalFoundries’ 130 nm 300mm RF technology platform (read about it here).

Looking forward, GF’s Rabbeni noted, “Significant R&D has been done in evaluating the application of SOI to 5G architectures, with very positive results. SOI holds great promise in delivering on the key requirements of 5G systems.”

TowerJazzPanasonic_RFSOI_300mm14

Courtesy: SOI Consortium and TPSCo

Also at the Tokyo event, Kenji Tateiwa, General Manager of R&D Strategic Planning for TPSCo (that’s TowerJazz/Panasonic), gave a great presentation on 300mm RFSOI Development toward IoT Era. 300mm RF-SOI, he noted, “has room to run.”

European Program Pushes Innovation Pipeline

For Soitec, of course, work on future generations of RF-SOI substrates continues unabated. You can be sure they’ve got a product roadmap focused on continued innovation and cost effectiveness for future mobile communication markets.

But in addition to working on its RF-SOI roadmap internally, Soitec is leading an international program to further develop the technology in collaboration with 16 partners from five European countries, representing the entire electronics value chain from raw materials to finished communication products. The REFERENCE Project, awarded in a call for projects by the Electronic Components and Systems for European Leadership (ECSEL) group ─ aims to create a European competitive industrial ecosystem based on RF-SOI.

Over the next three years, the REFERENCE Project expects to innovate new materials, engineered substrates, processes, design, metrology and system integration that pave the way for 5G wireless communications. The R&D and demonstration objectives for 4G+/5G technologies include Soitec’s development of RF-SOI substrates, and the production of RF-SOI devices at two major European semiconductor foundries. These advances will contribute to RF-SOI’s growing use in three targeted applications: cellular communications/the Internet of Things (IoT), automotive and aeronautics , including pioneering new frequency bands.

Soitec is at the forefront of European innovation and we are very happy to be part of this very important European research project involving key partners beyond our direct customers,” said Nelly Kernevez, partnership director at Soitec. “This initiative allows us to build the European Union’s RF community, consolidate our vision of what the future can be, and leverage proven material technology to create RF communication solutions for tomorrow.”

The wireless world will keep progressing by leaps and bounds over the next few years. And it’s looking like ever-advancing RF-SOI substrates will be the springboard. Stay tuned!

Now also on 300mm wafers and headed for 5G and IoT, RF-SOI’s going strong and stronger (>20 billion chips to date) – Part 1 of 2

Soitec, the industry’s leading supplier of SOI wafers recently announced it’s in high-volume manufacturing of a 300mm version of its wildly successful RFeSI line (see press release here).

What’s it all about? FEMs. RF front-end module – aka FEM – chips handle the back-and-forth of signals between the transceiver and the antenna. FEMs built on advanced SOI wafers are found in virtually every smartphone. Until now, the starting SOI wafers for all those RF FEMs were 200mm in diameter. But with demand continuing to increase, and the RF-SOI prospects for 4G/LTE-A (and then 5G) being very bright indeed, the bigger wafers were needed.

(Bear in mind that these RF-SOI wafers are not at all the same kind of wafers used in the RF and analog parts of an FD-SOI SOC. But because there’s still a fair amount of confusion about this, my ASN post, RF-SOI vs. FD-SOI with RF – What’s the difference? from a few months back sorted it out. If you missed it or you’d like a quick refresher, click here to read it.)

So, back to this announcement about the 300mm version of the RFeSI substrates. As the SOI wafer leader, Soitec’s got a lot of proprietary manufacturing technologies, and a boatload of experience with 200mm RF-SOI. High-volume manufacturing of 300mm SOI wafers isn’t new to them, either, since they’ve been doing that for over a decade.

Courtesy: Soitec

Courtesy: Soitec

But latest additions to the line, the advanced RFeSI90 wafers, required some really significant innovations. Soitec teamed up with UCL (you can read about that here) a few years ago on a breakthrough approach to SOI wafers for RF. This has opened the door for new enhancements that enable more highly integrated ICs for 4G/LTE-Advanced communications and the next generation of wireless technologies, including 5G.

20 billion RF-SOI FEMs, and counting

It so happens that the RFeSI 300mm wafer announcement comes just as Soitec reports that they’ve sold over a million 200mm RF-SOI wafers since 2009. Those million RF-SOI wafers have yielded about 20 billion FEMs. That means Soitec’s RF-SOI substrates are now integral in manufacturing antenna switches, antenna tuners, as well as some power amplifiers and WiFi circuits for the smart phone and related mobile markets. In fact they’re used by all the leading RF semiconductor companies to address cost, performance and integration needs for 3G and 4G/LTE mobile wireless.

Soitec_Aspar

Bernard Aspar, SVP Communications & Power BU, Soitec

Bernard Aspar, Sr. VP of Soitec’s Communication & Power Business Unit, is particularly pleased with their RF success. “The widespread use of Soitec’s materials technology in existing 3G and 4G portable communications demonstrates the important role of RF-SOI in high-volume, cost-sensitive applications such as cellular phones, tablets and other fast-growing markets involving mobile internet devices,” he said. “Now the high-volume availability of our newest 300mm RF-SOI offering enables our customers and their customers to continue to deliver higher performance while giving them access to foundries’ larger global production capacities and more manufacturing flexibility.”

200mm grows, too

To be sure, 200mm is still going strong and stronger, so Soitec is also increasing its 200mm production capacity. What’s more, last fall Soitec teamed up on a 200mm wafer manufacturing deal with Shanghai-based Simgui, which uses Soitec’s Smart CutTM technology to produce SOI wafers for its own RF, power and automotive customers in China, as well as manufacturing on an OEM basis for Soitec customers worldwide (read about that here).

Meanwhile, over the past 18 months Soitec has been delivering 300mm RFeSI90 wafer samples for product qualification. They note that key partnerships with fabless semiconductor companies and foundries have been instrumental in achieving the production milestones and outstanding performance levels of Soitec’s new 300mm RF-SOI product. In fact to make sure that customers get the performance they need, last year Soitec engineers even developed a way to predict the performance their wafers would provide (if you missed it, you can read more about that here).

To find out why some of the leading foundries and chipmakers have chosen to go with a 300mm RF-SOI wafer solution, and what’s in the RF-SOI substrate innovation pipeline, click here to read part 2 of this article.

China Design Conference (April 2016) Adds RF-SOI Design Track

EdiCon16EDI CON China 2016, taking place April 19-21 in Beijing at the China National Convention Center (CNCC) will feature a keynote talk by GlobalFoundries‘ Peter Rabbeni, Sr. Director, RF BU Business Development & Product Marketing. The talk, entitled, “RF SOI: Revolutionizing Radio Design Today and Driving Innovation for Tomorrow”, will kick off the newly added RF-SOI Technology Track. The SOI Track will also feature talks and workshops from Peregrine Semiconductor, TowerJazz, Simgui, AnalogSmith and Shanghai Jiao Tong University. The talks will cover substrate engineering, design enablement, CMOS power amplifier design techniques and highly integrated control devices.

Mr. Rabbeni’s keynote talk will cover how there has been dramatic growth in RF SOI over the last several years in its continued march in driving performance improvement, cost reduction and architecture innovation between the transceiver and the antenna in mobile radios. No other radio technology in recent memory has had the impact that RF SOI has had in this respect. With standards becoming increasingly more challenging and the pending introduction of 5G, RF SOI is expected to continue to play an important role in the development of innovative architectures. His presentation will explore where we have been, why and where we may be headed with this technology. Substrate engineering and SOI device technology is reviewed in detail in Microwave Journal’s October 2015 cover story at http://www.microwavejournal.com/articles/25255.

More information is available at www.ediconchina.com.

RF-SOI Innovator JP Raskin (his team’s work is in your smartphone) Awarded Blondel Medal

Raskin_BlondelMedal2015_RFSOI

Professor Jean-Pierre Raskin (right) receiving the Blondel Medal for his industry-changing work on RF-SOI. Jury president Professor Pere Rocal I Cabarrocas (left) of the Ecole Polytechnique – Université Paris-Saclay presented the prize.

RF-SOI substrate guru Jean-Pierre Raskin, whose team at UCL* has driven the technology behind the most advanced wafer substrates for RF applications, has been awarded one of the highest honors in electronics: the prestigious Blondel Medal. The technology he pioneered is now in virtually all the world’s smartphones, and used by just about every RF foundry on the planet.

Dr. Raskin’s team first demonstrated a radical new approach (dubbed “trap rich” at the time) for improving the RF performance of high-resistivity (HR) SOI substrates back in 2003. Teams from UCL and Soitec then worked together on the industrialization, making it commercially available in SOI substrates for RF applications.

ASN readers will recognize this work from a 2013 article Dr. Raskin co-authored, Soitec and UCL Boost the RF Performance of SOI Substrates.

The result was a new wafer substrate Soitec named eSI, for enhanced Signal Integrity, and it’s been wildly successful. In fact Soitec estimates that more than one billion RF devices are produced each quarter using their eSI wafers. It’s been used for 2G, 3G and now 4G and LTE. With the advent of LTE-Advanced (aka LTE-A), 5G and Wi-Fi 802.11.ac (aka Gigabit Wi-Fi), the latest iterations of the Raskin team’s technology are in Soitec’s most advanced eSI90 wafers.

The Blondel Medal is the highest honor awarded by the SEE (the French Society for Electricity, Electronics, IT and Communications Technologies). It recognizes a researcher under 45 years old who has authored works or recorded exceptional achievements that have contributed to the advancement of science in Information and Communication Technology.

~ ~

*UCL is the Université catholique de Louvain in Belgium. Click here to read more about Dr. Raskin’s research group.

Great FD-SOI start for 2016: Samsung, GF, Renesas, NXP/Freescale, ST, Soitec

Just a month into 2016 and we already have a raft of FD-SOI news from Samsung, GlobalFoundries, NXP/Freescale, Renesas and more. And of course RF-SOI continues ever stronger.

logo_soiconsortiumHere’s a quick update of what we’ve been seeing, starting with news from the recent SOI Consortium forum in Tokyo. Many of the presentations are now available on the SOI Consortium website – but keep checking back for more.

 

Samsung: 28nm FD-SOI hits maturity, mass production starts 1Q2016

Yongjoo Jeon, Principal Engineer in SEC Foundry marketing, Samsung, gave a talk entitled, The industry’s first mass-produced FDSOI technology for the IoT era, with single design platform benefits.

Here are his key messages with respect to 28nm FD-SOI:

  • The technology, which was qualified in 2015, is now ready for mass production, with the first commercial production set for 1Q2016.
  • Yield levels are excellent.
  • There were 12 tape-outs in 2015 in connectivity, security, games, set-top boxes, application processors for consumer and automotive, plus CMOS image sensors (aka CIS — for an excellent explanation of why FD-SOI is right for CIS and why leaders in this arena are considering it, see Junko Yoshida’s recent EETimes piece here).
  • The 16 tape-outs planned so far for 2016 expand to a wider range of automotive apps, plus we see the first in IoT and wearables, MCUs and programmable devices.
  • A production PDK for a version of 28nm FD-SOI with RF integration will be available in 2Q16.
  • eNVM (embedded non-volatile memory) will be ready in 2018.

For other key Samsung slides showing data on their success in manufacturability, check out EETimes.

 

GlobalFoundries: RF-SOI for 5G, FD-SOI Customers Engaged

Subramani Kengeri, VP of Global Design Solutions at GlobalFoundries talked about their 22nm FD-SOI, in his presentation Enabling SoC Innovations with 22FDXTM. He indicated that they’ve got over 40 customers engaged on it. Key points they’re hitting on that make them bullish on their prospects include:

  • FinFET-like performance and energy efficiency at 28nm cost
  • Ultra-low power consumption with 0.4V operation
  • Maximum flexibility in power/performance trade-off with software-controlled body biasing
  • Integrated RF cuts RF power in half and means designers don’t need an extra RF chip.
  • They’ll reach high-volume production by the middle of 2017.

For more on how GF see 22FDX as very well-positioned for IoT, see their Foundry Files blog. There’s also a really good piece in EEJournal by Byron Moyer entitled, A Non-FinFET Path to 10 nm – GlobalFoundries’ FD-SOI Alternative.

GF is of course also a dominant RF-SOI player, as seen in RFSOI: Defining the RF-Digital Boundary for 5G by Peter Rabbeni, Sr. Director RF Product Marketing and Business Development, GlobalFoundries. The presentation, which is available on the SOI Consortium website, notes that, “Significant R&D has been done in evaluating the application of SOI to 5G architectures, with very positive results,” so that, “SOI holds great promise in delivering on the key requirements of 5G systems.” (For an overview of GF’s RF-SOI position, see RF-SOI is IoT’s Future, and the Future in Bright on their Foundry Files blog.)

 

Renesas: in FD-SOI production at 65nm this year

Shiro Kamohara, Chief Engineer, Renesas Electronics Corp., lead off the presentations with Ultralow-Voltage Design and Technology of Silicon-on-Thin-Buried-Oxide (SOTB) CMOS for Highly Energy Efficient Electronics in IoT Era.

A Nikkei article reported from the conference that Renesas will be in mass production of 65nm FD-SOI – which they call Silicon-on-Thin-Box, or SOTB – for IoT products this year. Renesas reports the move cuts power to a tenth of what they’d seen in bulk. You can see the original article in Japanese here or a translated version here.

 

Soitec: wafers ready for mass adoption

Soitec_SOIsourcingIn the presentation Substrate maturity and readiness in large volume to support mass adoption of ULP FDSOI platforms, Soitec Sr. VP of Digital Electronics Group Christophe Maleville, Senior Vice President, Digital Electronics BU provided data on every conceivable aspect of SOI wafers for FD-SOI and RF-SOI. He explained adaptations in the company’s Smart CutTM manufacturing technology that achieve astonishing levels of uniformity and thickness – or rather, thinness! With new metrology, they can predict and protect against variability in devices. And they are now producing FD-SOI wafers for 28nm processes with uniformity of +/- 1 atomic layer.

 

ST: making the case

For analog/RF, RF/mmW and mixed-signal/high-speed designers, Andreia Cathelin, Senior Member of Technical Staff at STMicroelectronics explained how and why FD-SOI makes their lives easier. Her presentation, FDSOI Technology Advantages for Analog/RF and Mixed-Signal Designs drills down to the technical for these folks.

Pietro Maestri, ST’s RF Product Line Director presented ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration. (BTW, we had an excellent high-level article by ST when H9SOI_FEM was first announced, describing the challenges faced by designers of smartphone front-end modules (FEMs) and how their H9SOI_FEM solves them – read it here.)

For anyone wondering about the status of FD-SOI following the just-announced company reorganization, COO Jean-Marc Chery told EETimes’ Peter Clarke that they remain fully committed to the technology. As noted in the article (read the whole thing here), “Chery emphasized that, following the announcement of ST’s withdrawal from STB and home gateway markets and of a proposed redeployment of 600 engineers, the company is now focused on automotive and Internet of Things applications and that therefore FDSOI is a core manufacturing process. Indeed it could be argued that moving engineers familiar with FDSOI from the STB group into MCUs and automotive will help to proliferate the technology through the company.”

 

NXP/Freescale: Loving FD-SOI

In another recent EETimes article, Peter Clark reported from the NXP “Smarter World Tour” that the newly merged NXP-Freescale is very bullish on FD-SOI (see the full article here).

He cites Goeff Lees, the GM for the MCU part of the merged businesses, who especially likes 28nm FD-SOI for IoT and MCUs. Ticking off the reasons, he lists energy efficiency, cost, analog support, security, temperature control and lower leakage current. In fact, he says, “I believe all MCU vendors could move to FD-SOI.” Wow.

So stay tuned – here at ASN we’ve got contributions from NXP/Freescale, Synopsys, GlobalFoundries, Surecore and more at the top of the 2016 queue. Yes, it’s going to be a good year.

VLSI Research names Soitec CEO to 2015 All Stars of the Semiconductor Industry

Paul Boudre has been named CEO of Soitec.

Soitec CEO Paul Boudre

VLSI Research Chip Insider has named Soitec CEO Paul Boudre to its roster of 2015 All Stars of the Semiconductor Industry. (See the announcement here.)Soitec

Boudre was cited for “…successfully re-organizing Soitec back to its core business as a leading innovative engineered substrate supplier. His first year results are already astounding, with very high growth rates.” Getting FD-SOI and RF-SOI into the mainstream figured among the notable accomplishments that elevated him to these ranks.

Congratulations to Paul Boudre and the entire Soitec team for this important recognition by one of the industry’s leading analyst groups.

Interview (part 2 of 2): Leti Is a Catalyst for the FD-SOI Ecosystem. CEO Marie Semeria Explains Where They’re Headed

MarieSemeria_LetiCEO_©PIERREJAYET

Leti CEO Marie Semeria (photo ©Pierre Jayet/CEA)

From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie-Noelle Semeria shares her insights here in part 2 of this exclusive ASN interview as to what Leti’s doing to drive the ecosystem forward. (In part 1, she shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)

~ ~ ~

ASN: In which areas do you see SOI giving designers an edge?

MS: There is an advantage in terms of cost and power, so it’s attractive for IoT, for automotive, and more and more for medical devices. We see the first products in networks, in imaging, in RF. The flexibility of the design, thanks to the back bias gives another asset in terms of integration and cost. We consider that 28nm FD-SOI and 22nm FD-SOI are the IoT platforms, enabling many functions required by IoT applications. It’s a very exciting period for designers, for product managers, for start-ups. You can imagine new applications, new designs, and take advantage of engineered substrates combined with planar FD-SOI CMOS technology and 3D integration strategies to explore new frontiers.

Leti_MobileCR_JAYET_CEA

Leti’s home at the Minatec Innovation Campus in Grenoble boasts 10,000m² of clean room space. Here we see Leti’s mobile clean room, which they call the LBB ( for Liaison Blanc Blanc) carrying wafers from one clean room to another. (photo credit: P.Jayet/CEA)

ASN: What is Leti doing moving forward?

MS: Our commitment is to create value for our partners. So what is key for SOI now is to extend the ecosystem and to catch the IoT wave, especially for automotives, manufacturing and wearables. That’s why we launched the Silicon Impulse Initiative (SII) as a single entry gate providing access to FD-SOI IP and technology. SII is a consortium, gathering Soitec, ST, CMP, Dolphin and others, in order to beef up the EDA and design ecosystems. Silicon Impulse offers multi-project wafer runs (MPWs) with ST and GF as foundries based on a full portfolio of IPs. SII is setting up the ecosystem to make FD-SOI technology available for all the designers who have IP in bulk or in FinFET. To reach designers, we have set up events close to international conferences like DAC and VLSI, and we promote SII together with the SOI Consortium in San Francisco, Taiwan, Shanghai, Dresden….

The second way we are accelerating the deployment of FD-SOI technology in manufacturing is to provide our expertise to the companies who made the choice for FD-SOI technology. Leti assignees are working in Crolles with ST and in Dresden with GF to support the development of the technology and of specific IP such as back bias IP. The design center located in the Minatec premises is also open to designers who want to experiment with FD-SOI technology and have access to proof in silicon.

ASN: What role does Leti play in the SOI roadmap?

MS: The role of Leti is to pioneer the technology, to extend the ecosystem and to demonstrate in products the powerful ability of FD-SOI to impact new applications. Leti pioneered FD-SOI technology about 20 years ago. Soitec is a start-up of Leti, as well as SOISIC (which was acquired by ARM) in design. We developed the technology with ST, partnering with IBM, TI and universities. Now we’ve opened the ecosystem with GlobalFoundries and are considering new players. With the Silicon Impulse Initiative we are going a step further to open the technology to designers in the framework of our design center. We have had a pioneering role. Now we have to play a catalyst role in order to channel new customers toward FD-SOI technology and to enable new products.

Leti demonstrates that the FD-SOI roadmap can be expanded up to 7nm with huge performance taking advantage of the back biasing. Leti’s role is to transform the present window into a wide route for numerous applications requiring multi-node generations of technologies.

CEA002051_JAYET_CEA

Leti is located in the heart of Minatec, an international hub for micro and nanotechnology research. The 50-acre campus is unlike any other R&D facility in Europe. (Photo credit: Pierre Jayet/CEA)

ASN: Is Silicon Impulse strictly FD-SOI, or do you have photonics, MEMS, RF-SOI…?

MS: We started with FD-SOI at 28nm because it’s available: it’s here. But as soon as the full EDA-IP ecosystem is set-up, this will be open for sure to all the emerging technologies: embedded memory (RRAM, PCM,MRAM…), 3D integration (CoolCube, Cu/Cu), imaging, photonics, sensors, RF, neuromorphic technology, quantum systems….which are developed in Leti. Having access to a full capability of demonstrations in a world class innovation ecosystem backed by a semiconductor foundry and a global IP portfolio leverages the value of SII.

ASN: Can you tell us about the arrangement with GlobalFoundries for 22nm FD-SOI? How did that evolve, and what does it mean for the ecosystem?

MS: Yes, last month we announced that we have joined GlobalFoundries’ GlobalSolutions ecosystem as an ASIC provider, specifically to support their 22FDX™ technology platform. We have worked with GlobalFoundries over the years in the frame of the IBM Alliance pre-T0 program..

In joining the GlobalSolutions ecosystem, Leti’s goal is to ensure that GF’s customers – chip designers – get the very best service from FD-SOI design conception through high-volume production. This has been in the works for a while. At the beginning of 2015, we sent a team to GlobalFoundries’ Fab 1 in Dresden to support ramp up of the platform. And now as an ecosystem partner, Leti will help their customers with circuit-design IP, including fully leveraging the back-bias feature, which will give them exceptional performance at very low voltages with low leakage.

We will be able to help a broad range of designers use all the strengths that FD-SOI brings to the table in terms of ultra-low-power and high performance, especially in 22nm IoT and mobile devices. It really is a win-win situation, in that both our customer bases will get increased access to both our respective technologies and expertise. It’s an excellent example of Leti’s global strategy.

~ ~ ~

(This concludes part 2 of 2 in this Leti interview series. In part 1, Marie Semeria shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)

Interview: Leti Is the Moving Force Behind FD-SOI. CEO Marie Semeria Explains the Strategy (part 1 of 2)

From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie Semeria shares her insights here in part 1 of this exclusive ASN interview as to what makes Leti tick. In part 2, we’ll talk about Leti’s new projects and partnerships.

~ ~ ~

Advanced Substrate News (ASN): You’ve been CEO of Leti for a little over a year now, but those outside the Grenoble ecosystem are just getting to know you. Can you tell us a little about yourself and how you came to Leti?

MarieSemeria_LetiCEO_©PIERREJAYET

Marie Semaria, CEO, CEA-Leti

Marie Semeria (MS): My background is in physics. I did my PhD at Leti on magnetic memories. Then I joined Sagem in the framework of a technology transfer, followed by a start-up in field-emission display (FED). When I came back to Leti, I spent more than 15 years in different positions, mainly involved in microelectronics. This work included setting up the cooperation with the IBM alliance and technology program coordination, as well as preparing Leti’s future and setting up long-term projects and partnerships.

Then three years ago the CEO at CEA Tech asked me to join that organization. CEA Tech is the technology research unit of the CEA (the French Atomic Energy and Alternative Energy Commission). Leti is one of CEA Tech’s three institutes, which together are developing a broad portfolio of technologies for information/communications technologies, energy, and healthcare. So I extended what I did in Leti covering the whole domain of expertise of CEA Tech. Finally, in October 2014, I took over from outgoing Leti CEO Laurent Malier.

ASN: Can you tell us about Leti’s structure and budget? How are you different from the other big European research organizations?

MS: Leti is a leading-edge research institute. Our mission is to innovate: with industry, for industry. So 83% of our budget comes from partnerships funded by industry, or partially funded by industry and supported by the European Commission or local or national authorities. The other 17% is a grant from CEA. Our commitment is to create value. And so the business model of Leti is value-centric – value for its partners.

ASN: How do you decide what you’re going to work on? Is it your customers?

MS: Leti focuses its work on technological research. We are not an academic lab. We work closely with industry. So we share our roadmap with our industrial partners, which gives us feedback on their expectations, their visions, and helps us anticipate their needs.

Minatec_aerial_lores

Leti is located in the heart of the Minatec innovation campus in Grenoble. Minatec was founded by CEA Grenoble, INPG (Grenoble Institute of Technology) and local government agencies. The project combines a physical research campus with a network of companies, researchers and engineering schools. As such, Minatec is home to 2,400 researchers, 1,200 students, and 600 business and technology transfer experts on a 20-hectare (about 50-acre) state-of-the-art campus with 10,000 m² of clean room space. An international hub for micro and nanotechnology research, the campus is unlike any other R&D facility in Europe. (Photo: courtesy Minatec)

On another side, we have to be innovative ourselves, so we are very open to what is going on in the scientific world, sensing new trends, analyzing migrations, monitoring the emergence of new concepts. Therefore, part of Leti’s research is fed by partnerships with academic labs. And there are great opportunities to work with two divisions of CEA related to fundamental research in materials science and in life science. We have a partnership with Caltech in NEMS. We have partnerships with MIT, and with Berkeley in FD-SOI design. It is key for Leti to build on the relationships with the world’s leading international technological universities. We’re fully involved with the very active Grenoble ecosystem. There are great leveraging opportunities within MINATEC and MINALOGIC, with Grenoble-Alpes University and with the INPG engineering school in math and physics. The cooperation with the researchers at LTM is key in microelectronics and we will work with new teams at INRIA who will join us in the new software and design center located in MINATEC.

ASN: How much Leti activity is based on SOI?

MS: SOI is the differentiator for Leti in nanoelectronics. We pioneered the technology 30 years ago and boosted the diffusion and the adoption of the technology worldwide. This year we launched a new initiative named Silicon Impulse together with our partners ST, CMP, and Dolphin…to provide access to the FD-SOI technology and IP to designers. I would say about 50% of the resources of Leti is related to nano: nanoelectronics, nanosystems, nanopower, 3D integration, packaging, with silicon at the core.

All that we have developed in terms of CMOS, embedded memory, RF, photonics and MEMS, is based on SOI. So we’ve developed a complete, fully-depleted (FD) SOI platform for the Internet of Things, because you’ll need all these functions. Really, all the microelectronics activity of Leti has been based on SOI for a while now. It’s why today we continue to pioneer the technology. For example, we develop the substrates and we assess their performance with Soitec in the framework of a joint lab, which is a new strategy for both of us. We work with ST, with GlobalFoundries, to transfer the technology, to prove the substrate in their products. Now we are in a key position as a leading, innovating institute to turn our disruptive technology into products. So it’s really a turning point for us.

~ ~ ~

Here’s a quick “official” summary of Leti:

As one of three advanced-research institutes within the CEA Technological Research Division, CEA Tech-Leti serves as a bridge between basic research and production of micro- and nanotechnologies that improve the lives of people around the world. It is committed to creating innovation and transferring it to industry. Backed by its portfolio of 2,800 patents, Leti partners with large industrials, SMEs and startups to tailor advanced solutions that strengthen their competitive positions. It has launched 54 startups. Its 8,500m² of new-generation cleanroom space feature 200mm and 300mm wafer processing of micro and nano solutions for applications ranging from space to smart devices. With a staff of more than 1,800, Leti is based in Grenoble, France, and has offices in Silicon Valley, Calif., and Tokyo. Learn more at www.leti.fr. Follow them on Twitter @CEA_Leti and on LinkedIn.

Click here to read part 2 of this exclusive interview.

TowerJazz Cites Strong RF-SOI Growth as Driving force in TX Fab Acquisition

TowerJazz-Maxim-Fab

Citing strong RF-SOI demand, TowerJazz has signed an agreement to purchase Maxim’s 8-inch fab in San Antonio, Texas (shown here).

With the acquisition of Maxim’s 8-inch fab in San Antonio, Texas, TowerJazz plans to quickly qualify its core specialty technologies, including its advanced Radio-Frequency Silicon-on-Insulator (RF-SOI) offering, to serve the substantial growth in demand from its customers. (See press release here.)

The proposed purchase will expand TowerJazz’s current worldwide manufacturing capacity, cost-effectively increasing production by approximately 28,000 wafers per month. The availability of additional capacity is expected to be needed to serve TowerJazz’s current and forecasted robust customer demand. TowerJazz and Maxim expect to close the transaction in January 2016, subject to customary closing conditions.