Tag Archive wireless

ByGianni PRATA

Qorvo’s New SOI Components landing major wins at cellular base station manufacturers

Qorvo recently announced that new high-performance SOI components are landing major wins at cellular base station manufacturers. (Read the press release here.) Ideal for broadband communications systems, the highly integrated components significantly reduce external components while lowering cost, power consumption, and weight in wireless infrastructure, test and measurement, and defense and aerospace applications. (Qorvo was formed following the merger of RFMD and TriQuint.)

“These new SOI components feature the broadband performance our customers expect from Qorvo’s products,” said Sumit Tomar, general manager of Qorvo’s Wireless Infrastructure business unit. “With exceptional linearity, robust power handling, and no external components, this portfolio is already in demand, even in the sampling stage.”

ByGianni PRATA

Soitec and SITRI team up on RF-SOI, LTE-A/5G for China and more

SoitecSITRISOI wafer leader Soitec and SITRI (aka Shanghai Industrial µTechnology Research Institute) have announced a collaboration agreement. (Read the press release here.) They say the strategic partnership will strengthen their leadership in high-growth wireless communications and the global market for RF apps, with a special emphasis on the fast-developing Chinese RF ecosystem.

They’ll focus on developing RF-SOI using advanced circuit designs based on Soitec’s substrate materials and technologies.

“Experience shows that Soitec’s engineered substrates can optimize RF-SOI technology and applications in terms of both cost competitiveness and power efficiency. This strategic partnership will enable us to push the limits of RF circuits and meet future connectivity needs,” said Soitec CTO Carlos Mazure.

“Enhancing RF signal integrity is a key focus of the mobile communications industry as it builds toward 4G-LTE Advanced and 5G standards. We are excited to partner with Soitec in developing next-generation SOI communication solutions. It is consistent with SITRI’s mission to create a collaborative R&D and commercialization environment to catalyze the growth of advanced technologies,” said Dr. Charles Yang, president of SITRI.

ByGianni PRATA

GlobalFoundries Blogs that IoT Future Is Bright With RF-SOI, FD-SOI

A recent GlobalFoundries blog entitled RF-SOI is IoT’s Future, and the Future is Bright (read it here) says, “RF SOI is a win-win technology option that can improve performance and data speed in smartphones and tablets, and it is expected to play a key role in the Internet of Things applications as well.”

The blog touches on the full range of benefits of RF-SOI for front-end integration, resulting in, “… longer battery life, less dropped calls and higher data speeds.” It then goes on to cite complementary advantages of FD-SOI. Peter Rabbeni, GlobalFoundries director of RF Segment Marketing, notes that in FD-SOI, “dynamic control of Vdd and the use of well-bias techniques can not only help reduce overall power consumption but can be used as a means to optimize RF circuit operation. This is not something that can be easily done in bulk technologies.”

ByGianni PRATA

RF-SOI Key in MagnaChip IoT Plans

RF-SOI will play a key role in the IoT plans of analog and mixed-signal specialist MagnaChip (read the press release here). The company has launched a task force to address IoT. The statement says, “MagnaChip also offers 0.18 micron and plans to offer 0.13 micron Silicon on Insulator (SOI) RF-CMOS technologies, which is suitable for use in antenna switching, tuner and Power Amplifier (PA) applications. Switches and tuners are core components of wireless Front-End-Modules (FEMs) for cellular and Wi-Fi connectivity in IoT devices. MagnaChip’s CMOS based FEMs reduce manufacturing cost and time to market while providing competitive performance for multiband and multimode smartphones, tablets and other IoT devices.”

Commenting on the IoT opportunity, YJ Kim, MagnaChip’s interim Chief Executive Officer, said, “We believe there is tremendous growth opportunity in the IoT market and our participation is part of our overall strategy to broaden our product portfolio in new markets. MagnaChip’s IoT task force and business consortium with key business partners will reinforce our position as a key manufacturing service provider in the expanding IoT market.”

ByGianni PRATA

Hua Hong (“Grace”) Semi Launches New RF-SOI Tech Platform and PDK

hhgracelogoHua Hong Semiconductor of Shanghai (a pure-play 200mm foundry operated by HHGrace Semi) recently launched a 0.2μm RF-SOI process design kit (PDK) (click here to read the full press release). The 0.2μm RF-SOI technology platform has been successfully validated and is ready for customers product design and development, says the company. It is tailored and optimized for wireless RF front-end switch applications. The new PDK solution is developed from Cadence’ IC5141 EDA software, and integrates RF modeling and simulation platform such as PSP SOI and BSIM SOI. The company notes that the 0.2μm RF-SOI PDK offering provides convenience to designers who focus on optimizing both the RF performance and die size, while greatly shortening time-to-market.

Dr. Weiran Kong, Executive Vice President of Hua Hong Semiconductor said, “With the booming of mobile Internet and intelligent terminals in recent years, there are more and more applications of consumer electronics with the use of RF SOI design. 0.2μm RF-SOI technology is one of our focuses. With this new offering, we will actively help our customers to capture market opportunities. The technology is ideal for RF switch designs such as smartphones and connected devices of Internet of Things. Through adding 0.2μm RF SOI technology solution into our RF portfolio, we are able to provide customers with comprehensive, cost effective and high performance RF solutions, which also include RF CMOS, SiGe BiCMOS and embedded Flash technology with RF PDK.”

HHGraceFoundryThe Group currently has one of the largest 200mm wafer processing capacities in China through its three fabs in Shanghai, with an approximate total 200mm wafer manufacturing capacity of 129,000 wafers per month as of September 30, 2014.


How SOI wafers for RF predict LTE-A/5G device performance

Soitec has developed an innovative metrology and metric for ensuring that devices built on our latest SOI wafers for RF will meet the draconian demands of LTE-Advanced (LTE-A) and 5G network standards.

For smartphones and tablets to handle LTE-A and 5G, they need RF devices with much higher linearity than those running over the current 2G, 3G, 4G and LTE network generations. These next generation network standards require mobile devices to support more bands, higher frequency bands, and emission and reception on adjacent bands with downlink and uplink carrier aggregation. (Carrier aggregation refers to the simultaneous reception of multiple frequency bands to improve data throughput.)

Soitec recently announced eSI90, our newest generation of trap-rich, high-resistivity SOI wafers for LTE-A and 5G. eSI90 extends our existing line of eSITM (enhanced Signal Integrity) wafers, the first generation of which are currently being used by leading manufactures to produce more than a billion RF devices every quarter.

This article gives an overview of how Soitec developed a new metric using innovative metrology on its wafers in order to predict the RF performance of final devices manufactured on eSI substrates. (Readers wanting greater detail can also consult our complete white paper on the subject, which is freely available to download here.)

Wafer specs evolve to meet new standards

To address the different communication standards and functions used in front-end modules, Soitec, the leader in SOI technology, has developed two flavors of RF-SOI products – high-resistivity (HR)-SOI and Enhanced Signal Integrity TM (eSI) SOI – both of which are compatible with standard CMOS processes. While standard HR-SOI wafers (which we introduced over a decade ago) are capable of meeting 2G or 3G requirements, eSI SOI can achieve much higher linearity and isolation specifications, allowing designers to address some of the most stringent LTE requirements. (We detailed how advanced RF design challenges are solved by eSI wafers in a 2013 ASN article – you can still read it here.) This paves the way for integrating more functions on a device with better RF performance at competitive cost.


Soitec’s enhanced Signal Integrity™ (eSI) wafers integrate a trap-rich layer under the insulating BoX in a high-resistivity (HR) SOI wafer (Image courtesy of Soitec)


eSI wafers leverage the addition of a “trap-rich” layer to high-resistivity (HR) SOI wafers, an approach that was developed by UCL and Soitec (that project was covered in an ASN piece explaining the technical details at the time – you can read it here).


Change at all levels

The IIP3 linearity requirements for 3G are +65dBm. For LTE, they increased to +72dBm, and for LTE-A, they are over +90dBm. For RF designers, this has added substantially to the complexity of RF Front-End Modules (FEMs), and entails multiple changes for each of the main functions: switches, power amplifiers, power management and antenna tuners.


Example of Front-End Module Block Diagram for 3G


Example of Front-End Module Block Diagram for LTE


These latest front-end modules need to support more bands, higher frequency bands from 700 MHz to 3.5 GHz, larger bands from 20 MHz to100 MHz and carrier aggregation downlink and uplink, sometimes on adjacent bands. This means:

  • A proliferation of switches on top of the antenna switch including diversity, power-mode and antenna-swapping switches
  • Advanced, tunable power-amplifier architectures to achieve compact and cost-effective multi-mode, multi-band transmission in a single broadband power amplifier
  • Advanced power management: with an envelope-tracking system approach, the efficiency of broadband power amplifiers will be close to or as good as that of single-band power amplifiers
  • Advanced wide-band antenna: with an antenna-tuner system performing either impedance matching and/or aperture tuning, an antenna can efficiently cover bands with frequencies from 700 MHz to 3.5 GHz with optimum efficiency and a smaller footprint

To meet the required performance, many changes are happening at all levels, from systems, architectures, design, manufacturing processes, devices – right down to where it all starts: the substrates. The substrates on which RF devices are manufactured have a significant impact on the level of performance that the final chips will be capable of achieving.

Characterizing eSI wafers

To quantify the performance designers can expect from an eSI SOI substrate, Soitec has now developed an innovative characterization method based on spreading resistance profiling (SRP), which can predict the 2nd harmonic distortion (HD2) performance of a coplanar waveguide. This solution is used today throughout the Soitec eSI product line to ensure the substrates will enable the expected RF performance in the finished devices.

We predict the RF harmonic distortion performance of the substrate immediately after the eSI SOI substrates are fabricated and before any devices are manufactured on them. This prediction is provided through a metric we call the harmonic quality factor (HQF).

HQF correlates with the second harmonic distortion generated from a 900-MHz signal applied to a coplanar waveguide (CPW) deposited on the substrate.

The CPWs are implemented on sample test wafers by depositing aluminum metal lines on the buried oxide of eSI SOI wafers after the Smart Cut process has been completed and the top silicium removed.

Then a 900-MHZ fundamental tone is applied on one end of the CPW line and the HD2 signal is measured at the other, providing a value of the HD2 generated by the substrate. Then, using the same wafers, a Spreading Resistance Profiling (SRP) technique measures the resistivity of the material at different depths under the buried oxide.

Next, we use a proprietary algorithm to compute the series of measures. The algorithm, tuned to match various HD2 values, takes into account the resistivity of the substrates weighted by the depth of the measure, and gives us the HQF.

Soitec has implemented this metrology on its production eSI SOI wafers and is sampling products to carry the HQF measurement.

To address different market requirements, we set our HQFmax specification at -80 dBm for eSI-G1 (first-generation eSI product) and at -90 dBm for our eSI90 (second-generation eSI product).


HQF specifications for Soitec’s 1st and 2nd generation eSI products (eSI-G1i and eSI90, respectively) correlated with linearity requirements.


HQF metrology, conducted at the substrate level, provides a reliable measure of the finished devices’ RF performance. It is now being used by Soitec to report the expected RF linearity performance of ICs manufactured with RF-SOI substrates.

As a solution addressing the current and next generation of RF standards, eSI SOI wafers are enabling this market by meeting some of the most difficult LTE and LTE Advanced linearity requirements. Soitec is able to provide its customers with the eSI SOI substrates that meet their desired level of RF performance.


LTE-A/5G: Bring it on. Next-gen Soitec eSI90 wafers predict & improve RF performance.

The folks at SOI wafer maker Soitec have announced an amazing update to their RF wafer line-up, with what they’re calling their eSI90 substrate (read the press release here). As you might expect, it improves on their terrifically successful line of substrates for the RF chips in smartphones and other mobile devices. And now with this latest substrate, they’ve developed metrology that allows designers to predict the linearity of finished RF devices, ensuring they meet the demands for next-gen networks.

SOI wafers for RF are mainly 200mm (8”) in diameter. Soitec CEO Paul Boudre says they’ll continue to run at full capacity in 2015-2016. Additional wafers will also be available through Soitec’s partnership with Simgui in China.

(Courtesy: Soitec. (C) photo Christian Morel / www.morel-photos.com)

(Courtesy: Soitec. (C) photo Christian Morel / www.morel-photos.com)

How successful is this line? “Today, we estimate that more than one billion RF devices are produced each quarter using our eSI wafers,” says Dr. Bernard Aspar, senior vice president and general manager of Soitec’s Communication & Power Business Unit.  That’s for 2G, 3G and now 4G and LTE.

But with the advent of LTE-Advanced (aka LTE-A), 5G and Wi-Fi 802.11.ac (aka Gigabit Wi-Fi), RF designers need a whole lot more linearity in finished devices. That’s where eSI90 comes in.

Why? We’re looking at a 10x increase in smartphone data traffic (much of it due to high-def video) between 2013 and 2018, with average connection speeds jumping from 4Mbps to 7 Mbps.


SOI wafers. (Courtesy: Soitec)

But to achieve the throughput needed, designers are faced with draconian linearity requirements and far more complex front-end modules (FEM). The wafer substrate they start on has a major impact on the performance level of the final devices.

Seeing this coming, a few years ago Soitec teamed up with experts at the Université catholique de Louvain (UCL). Leveraging Soitec’s Smart Cut™technology, they developed and industrialized the addition of a “trap-rich” layer in high-resistivity (HR) SOI wafers (if you missed it, they wrote an excellent ASN piece explaining the technical details at the time – you can read it here).

The first generation of these trap-rich HR SOI wafers, which Soitec called eSI (for enhanced Signal Integrity), was a tremendous success from the get-go. Designers loved that the wafers enabled relaxed design rules, reduced process steps and gave them highly competitive performance and die cost, including a smaller area per function (well explained here).

So here’s what’s new about the new eSI90 wafers: they exhibit higher effective resistivity than first-generation eSI wafers, enabling a 10-decibel (dB) improvement in linearity performance in RF front-end modules to address the stringent new requirements of LTE-A smart phones.

Those eSI90 SOI wafers are designed to improve the RF performance of mobile communication components such as high-linearity switches and antenna tuners that are integrated in high-end smart phones for LTE-A networks using carrier aggregation. This enables multiple LTE carriers to be used together, providing higher data rates to enhance user experience.

To ensure that the new wafers would deliver on their promise, the Soitec team developed a new metrology metric, the Harmonic Quality Factor (HQF), to predict the expected RF linearity of finished ICs. We’ll have a more in-depth explanation of how this works coming up in ASN from the Soitec team. But for now, designers will appreciate that HQF correlates with the second harmonic distortion value of a coplanar waveguide deposited on the substrate. The new eSI90 wafers’ HQF maximum value is set to -90 decibel- milliwatts (dBm) compared to -80 dBm for first-generation eSI substrates. The lower limit on eSI90 wafers enables chipmakers to take advantage of design and process improvements to increase the RF performance of their chip designs and to meet MIMO (Multi-Input Multi-Output) and Carrier Aggregation LTE-A requirements, providing faster data connections.

The new eSI90 substrates are already under evaluation at leading chipmakers and foundries. Production-ready samples are now available from Soitec.

When it comes to next-gen mobile design, innovation really does start at the substrate level.


Successful RF-SOI 2014 International Symposium Held in Shanghai

A very successful international workshop on RF-SOI was held in Shanghai earlier this fall.  Jointly organized by industry leaders, it brought together world-class players in RF to discuss the opportunities and challenges in rapid development of RF applications.Sponsors included the SOI Industry Consortium, the Chinese Academy of Sciences (CAS) / Shanghai Institute of Microsystem and Information Technology (SIMIT), Shanghai Industrial μTechnology Research Institute Co.,Ltd. (SITRI) and VeriSilicon.

The first talk, given by Dr. Xi Wang, Academician of CAS and Director General of SIMIT, covered China’s huge market prospects for RF applications. RF-SOI, he noted, is an area in which Shanghai Simgui Technology Co.,Ltd. ,  a spin-off company from SIMIT,  and French SOI wafer manufacturer Soitec are working closely to explore the market opportunities now. He also presented some of the latest research findings and the industry dynamics in this field.

Xi Wang, Academician and Director General of the Shanghai Institute of Microsystem and Information Technology (SIMIT) /Chinese Academy of Sciences (CAS) giving the first talk at the 2014 International RF-SOI Workshop.

Xi Wang, Academician and Director General of the Shanghai Institute of Microsystem and Information Technology (SIMIT) /Chinese Academy of Sciences (CAS) giving the first talk at the 2014 International RF-SOI Workshop.


Next, Handel Jones, CEO of IBS, gave a detailed analysis of the markets for smart phones and tablet PCs and other mobile consumer applications. These are strong drivers of the huge market opportunity and demand for chips based on RF-SOI technology. (Click here to view his presentation.)


(Courtesy: IBS)

(Courtesy: IBS)

This workshop also featured presentations by ST, GlobalFoundries and SMIC, as well as several important RF-SOI platform providers.

Mark Ireland, Vice President of Strategy and Business Development at the IBM Microelectronics Division, noted that that IBM first began offering RF-SOI manufacturing in 2006.  He explained the key role RF-SOI plays in redefining chips for mobile applications, where integration and performance are key. (Click here to view his presentation.)

Laura Formenti, Infrastructure and RF-SOI Business Unit Director at STMicroelectronics, gave a detailed analysis of RF-SOI. She covered the advantages of RF front-end integration and introduced ST’s H9SOI_FEM technology platform. (Click here to view her presentation.)

Paul Colestock, Sr. Director of Segment Marketing at GlobalFoundries shared specifics and the latest developments in the 130nm RF-SOI technology platform, UltraCMOS 10.


The room was full at the Shanghai RF-SOI Workshop 2014

The room was full at the Shanghai RF-SOI Workshop 2014


Herb Huang, Sr. Director Development, Technology R&D at SMIC, China’s largest foundry, addressed SOI in RF switches. He shared details on SOI NFETs for enhanced performance, and on CMOS MEMS RF filters. SOI CMOS will facilitate integration of switches (SW), power amplifiers (PA), envelope tracking (ET) and antenna tuning (AT) in SoCs. The foundry provides not only device-level processes but also support for high-performance system-in-package (SiP) solutions at the wafer level.

Professor Jean-Pierre Raskin of the Catholic University of Leuven (Belgium) and Bernard Aspar, General Manager of Soitec’s Communication & Power Business Unit presented detailed technical analyses of SOI substrates.  They covered the influence of substrates on RF signal integrity and the key role they play in improving RF performance thanks to the enhanced Signal Integrity (eSI™) High Resistivity SOI substrate.  (Click here to view the UCL presentation, and here to view the Soitec presentation.)

James Young, VP of Engineering, FES Si Platform Engineering at Skyworks focused on RF and wireless semiconductor design. In particular he addressed mobile phone design, including PA, ET and APT (Average Power Tracking). He gave performance comparisons and analysis for SOI/CMOS vs. GaAs devices.  (Click here to view the presentation.)

Dr. Yumin Lu, VP of the Shanghai Industrial μTechnology Research Institute Co.,Ltd. elaborated on how 4G wireless communications brings new challenges for RF front-end modules and components. RF-SOI has become a mainstream technology for antenna/switches. There is also significant potential for RF-SOI to make further inroads in applications such as tunable components (including antennas, PAs, filters/duplexers, etc.). (Click here to view the presentation.)


Roundtable Discussion at the 2014 International RF-SOI Workshop in Shanghai

The final panel discussion session on the “China RF market” started a lively debate. Topics included the specificities and drivers of the China RF market, Chinese foundry capacity, the RF-SOI supply chain, RF front-end module (FEM) system packaging and system integration trends, and LTE and WiFi common platforms on RF-SOI substrates.  Audience members had questions about device design. The need for the industry to establish a broader ecosystem was a common theme.

 ~ ~ ~

Editor’s note: This article was first posted in Chinese at Shanghai Institute of Micro-Technology Industry Views. You can see the original hereMany thanks to Xi Wang, Academician and Director General of the Shanghai Institute of Microsystem and Information Technology (SIMIT) /Chinese Academy of Sciences (CAS) for his permission to translate/adapt and reprint it here in ASN.


Is China Interested in FD-SOI? You bet.

At the recent FD-SOI Forum in Shanghai, the IoT (Internet of Things) was the #1 topic in all the presentations.

The event was sponsored by the SOI Consortium, the Shanghai Institute of Microsystem and Information Technology / Chinese Academy of Sciences (SIMIT/CAS), and VeriSilicon. By all accounts it was a great success. Speakers included experts from Synopsys, ST, GF, Soitec, IBS, Synapse Design, VeriSilicon, Wave Semi and IBM (see below for key slides and links to the full presentations). The goal was to gather IC industry decision makers, technology owners, opinion leaders and market analysts to exchange and assess the opportunities that FD-SOI technology brings in terms of ultra-low power operation at high performance for mobile and IoT.


A panel discussion during the SOI Consortium's Shanghai FD-SOI Forum brought whole ecosystem onto same stage – a clear sign of FD-SOI becoming mainstream solution. (Courtesy: SOI Consortium)

A panel discussion during the SOI Consortium’s Shanghai FD-SOI Forum brought whole ecosystem onto same stage – a clear sign of FD-SOI becoming mainstream solution. (Courtesy: SOI Consortium)

Here are some of the points made by the speakers:

  • FinFET is a tough (Intel is running 15 months behind) and capex consuming technology (exponential situation in terms of costs), so not everybody will be able to go for it
  • FD-SOI will be a game changer
  • the FD-SOI ecosystem is now ready but industry still seems a bit too conservative to get started
  • FD-SOI is a great opportunity for China to take the lead
  • need a big fabless house with a high-volume application and then foundries building capacity
  • promising outlook: designs are underway; in 6 to 9 months there could be significant volumes. It is no longer a question of why FD-SOI – now we are at when FD-SOI.
  • 28nm will be a long lifetime technology node (2012-2024)
  • IoT: a good opportunity for FD-SOI
  • work is being done by the ecosystem to improve FD-SOI IP
  • FD-SOI is not only for 28nm but also 20/22nm and 14nm (ST discussed its 14nm FD-SOI)
  • the industry acknowledges ST and Soitec’s commitment to developing FD-SOI technology

We know that FD-SOI 28nm has moved into the manufacturing and volume production phase. It offers the chip industry the unique features of being able to fabricate at competitive cost, ultra low power, high speed ICs. It is a game changer technology platform that brings new powerful elements to the designers and a strong differentiation potential at IC and system level. But the speakers acknowledged that challenges remain, in particular that there’s a need for a greater commitment from industry and for very big customers (but that’s going to change).


The presentations

Here are brief summaries of the presentations. Click on the presentation names to download the full pdfs, or on the slides for enlarged images.

Market Overview and Opportunities by Handel Jones, CEO, International Business Strategies

Starting from a bird’s-eye view of the world, this presentation then zooms down deep into the nitty-gritty of chip manufacturing costs. Considering the various technology options for current and future nodes, it looks at costs per gate and per wafer, costs for design and for tooling, yield impact and fab life. The world’s largest chip consumer, China currently imports about 90% of the chips used there. The government has targeted 2020 as the year by which Chinese semiconductor companies should be supplying 40% of semiconductors consumed in China. IBS sees FD-SOI as the most astute choice, especially for IoT.

Slide 5 from the IBS presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: IBS)

Slide 5 from the IBS presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: IBS)


FD-SOI Technology by Laurent Remont, VP Technology & Product Strategy, STMicroelectronics

This presentation gives an overview of FD-SOI technology, roadmaps and markets. One of the points made is that 28nm will be the longest process generation with the highest volume manufacturing. FD-SOI extends the 28nm offering with improved power and performance rivaling existing 20nm bulk.

Slide 13 from the first ST presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: ST)

Slide 13 from the first ST presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: ST)


Design with FD-SOI, Innovation Through Collaboration by Marco Casale-Rossi, Product Marketing Manager, Synopsys

The Synopsys presentation detailed FD-SOI/EDA readiness, with illustrations from an ST design. Among the many impressive results, time-to-good-floorplan was reduced 10x, and leakage was reduced by 59% through advanced EDA in the flow.

Slides 20 and 34 from the Synopsys presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: Synopsys and ST)

Slides 20 and 34 from the Synopsys presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: Synopsys and ST)


Designing with FD-SOI for Power Efficiency by Haoran Wang, Associate General Manager, Synapse Design China

Synapse Design is an industry leader in design services for most top tier semiconductor and system companies around the world. They have been working on designs in FD-SOI for over four years. In fact, they’ve already had four tapeouts in FD-SOI and are working on three others. The presentation noted that “…FD-SOI has more degrees of freedom than bulk” conferred by device physics. They recommend starting with a deep power analysis at RTL, looking carefully at performance requirements vs. battery life. They conclude, “At 28nm, FDSOI does show the benefits of speed/power advantage. It is a viable solution from technology point of view and easy to be integrated in current design flow.”


Slide 2 from the Synapse Design presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: Synapse Design)

Slide 2 from the Synapse Design presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: Synapse Design)


Leveraging FD-SOI to Achieve Both Low Power AND High Speed by Pete Fowley, CEO, Wave Semiconductors

Wave is a fabless semiconductor startup “commercializing a programmable solution addressing power, concurrency, design time, design cost, and deep submicron challenges facing the semiconductor market.” The founders come from a veritable who’s who industry background* (the CEO was one of the first members of Apple’s original Mac chip design team). They bill their FD-SOI based Wave Threshold Logic (WTL) as their “secret sauce”. WTL can use both very fast flip-well LVT devices with Forward Body Bias (FBB) and Standard VT devices that have very low leakage through very high Reverse Body Bias (RBB). According to Wave, “WTL‐ BB represents a unique differentiator for FD‐SOI: enabling significant performance and power advantages over bulk processes. This strategic advantage will persist into deeper nodes.” Clearly one to watch!


The FD-SOI Technology for Energy Efficient SoCs by Giorgio Cesana, Director of Marketing, STMicroelectronics

Here ST gives a FD-SOI primer, explaining the technology, design considerations and Forward Body Bias (FBB) use and results. Examples from both fast CPU/GPU and ultra-low power designs are given.

Slide 19 from the second ST presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: ST)

Slide 19 from the second ST presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: ST)

SOI Ecosystem – Strategic Opportunity for China by Tom Reeves, VP Technology Alliance, IBM

The SOI ecosystem is a central theme in this presentation. It has a long history of producing successful ICs, and the SOI enabled device structure pipeline continues through 7nm. IBM sees big opportunities for China in mobile, automotive, industrial, IoT, wearable and other More-than-Moore apps. The call to action is clear: now is the time for China to accelerate the building of its SOI ecosystem.

Slides 3 and 7 from the IBM presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: IBM)

Slides 3 and 7 from the IBM presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: IBM)

Foundry Business Opportunities by Paul Colestock, Sr. Director of Segment Marketing, GlobalFoundries has not yet been posted as of this writing. But keep checking back – it should be there soon.

Also, look for another ASN post on the Shanghai 2014 RF-SOI Workshop coming up shortly.


Special thanks to the folks at the SOI Consortium for their help in compiling details for this piece.

* A tip of the hat to Eric Esteve at Semiwiki for first pointing this out in his recent piece on Wave Semi’s technology, which you can read here.

ByGianni PRATA

Soitec receives Sony’s Best Partnership Award for its support with RF-SOI substrates

(Courtesy: Sony and Soitec)

(Courtesy: Sony and Soitec)

SOI wafer leader Soitec was awarded the Best Partnership Award by Sony Semiconductor. Soitec earned the recognition for outstanding support that has contributed to Sony’s success in the RF semiconductor market.

Soitec’s high-resistivity silicon-on-insulator (HR-SOI) wafers have long been a favorite of RF designers for 2G and 3G switches. But the company’s latest eSi substrates has taken off like wildfire, and are now used by all the major companies that make RF chips for smart phones.  The eSI wafers enable much higher linearity and isolation, helping designers to address some of the most advanced LTE requirements at competitive costs.  You can read more about the technical details of the wafers and how they were developed here and how they solve key challenges here.

“We are very honored to receive this award from Sony recognizing the long partnership between our companies,” said Bernard Aspar, senior vice president and general manager of Soitec’s Communication & Power Business Unit. “It demonstrates Soitec’s commitment to deliver the enabling substrates that support Sony’s RF devices business.”