Achieving High Throughput Inspection of Multiple SOI Wafers
Posted date : Dec 7, 2005

Historically, chipmakers conducting incoming quality control (IQC) on SOI wafers used for advanced logic devices are challenged in inspecting these substrates as efficiently and effectively as their bulk counterparts.

The prevailing inspection process utilizes visible light inspection systems. However, these systems often require specific recipe setups and tool calibrations for each SOI wafer type and thickness. This has hampered the ability of chipmakers to establish consistent results at a standard level, and it has also resulted in slower time to results. What chipmakers need in order to accurately and quickly qualify their SOI wafers is a high-throughput capability to inspect SOI substrates, ideally using the same recipe and calibration across multiple wafers.

For years, KLA-Tencor has worked with multiple advanced logic fabs and SOI wafer suppliers to develop and improve the inspection capability to accommodate multiple SOI wafers types. The approach has been to use UV inspection technology, and take advantage of the way that the scattering behavior of illuminated surface defects on SOI wafers “mimics” that of the bare silicon wafers. By leveraging the innovative UV laser system in the Surfscan SP2 unpatterned wafer inspection system, KLA-Tencor has been able to generate complete surface quality data with accurate defect sizing (based on latex sphere equivalent) for a SOI wafer. This methodology can now be accomplished consistently across multiple SOI wafers with a single recipe and calibration level, using the inherent sensitivity of the SP2 to surface defects. The system has even demonstrated as high as 60 nm sensitivity on SOI wafers at high throughput mode. This methodology is enabling the industry to meet the single recipe and calibration criteria for efficient IQC.

Our studies have shown optimal results, allowing the recommendation of production inspection recipes at comparable and common thresholds to bare silicon wafers. This methodology, advantageous to both wafer and IC manufacturers, is a big step forward, resulting in time and cost savings for the qualification of SOI wafers.

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