For this 3-part series, ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 3, we’ll talk about the ecosystem. (In part 1 we talked about technology readiness, and in part 2, we talked about design.)
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ASN: Let’s talk a little more about IP availability.
Axel Fischer: The availability of IP is key for engaging these market segments. The technology itself is ready. The gating item often is the IP element.
Kelvin Low: The IP element is broadly ready. But we’re not stopping there. We’re enhancing the IP and adding on new suppliers. Most of them we can’t name yet just because of timing. But we can confidently say that multiple new IP suppliers are coming online, and many more have started to inquire about how they can get onboard.
ASN: In terms of the ecosystem, what remains to be done?
KL: The ecosystem can never end. Enhancements will always be welcome. More support – there are so many other EDA software companies out there available. We will enable them if there is a customer behind them. IP are dictated by the standards. As long as the product requires that, we’ll continue to look for partners to develop the IP.
KL: Back to one of the strategic decisions we made. We have immediately made available what ST Micro has in terms of IP portfolio to our customers. Then continuously build this ecosystem according to the new customers that we’re acquiring. ST Micro has developed these IPs for their own internal products, and they were gracious enough to allow these IPs to be opened up to be used by all customers without restriction.
As a group, as an ecosystem, we have to be more proactive in educating the market. What we’ve seen so far, whether it’s an initiative by Leti or an initiative by the SOI Consortium, these are very helpful. Now you have so many more knobs that you can play with, for designers we have to prepare all these PVT – which is process, voltage, temperature, and timing points so they can actually use it. It’s just a matter of preparation needed from our end, working with the ecosystem. The EDA tools must be optimized to make it as seamless, as transparent as possible.
ASN: Any closing thoughts?
KL: 28FDSOI is real. Samsung is committed. The technology is qualified already. The ecosystem is ready and expanding. This is working stuff. It’s not a powerpoint technology.
This is the last installment in ASN’s 3-part interview with Samsung on their 28nm FD-SOI foundry offering. If you missed the other parts, you can still read part 1 about technology readiness (click here), and part 2 on design considerations (click here).
For this 3-part series, ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 2, we’ll talk about design. (In part 1, we talked about Samsung’s technology readiness. In part 3, we’ll talk about the ecosystem.)
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ASN: Let’s start by talking about value. What do you see as the key advantages of 28nm FD-SOI?
Kelvin Low: FD-SOI is wide-ranging. What I mean by this is for the designers, there are many design knobs available that you can use to achieve either high performance or ultra low power. That’s a an extremely valuable and important proposition. The wide dynamic performance-power range is achieved with FD-SOI’s body biasing ability. Though bulk technologies allow body biasing, it has a comparatively much narrower range.
Another key benefit is the super analog gain and properties of FD-SOI. I think moving forward, we’ll probably start to see more customers that are analog-centric. Later on, we’ll see this as one of the key value propositions of FD-SOI. Today, there’s still a lot of digital customers that we’re engaged with right now. The analog customers are still not yet aggressively migrating to [[more advanced]] technology nodes, but when they come, this will be an important distinction in FD-SOI vs. bulk.
Another important distinction not related to power-performance-area is the robustness of the reliability. This is a well-proven fact that FD-SOI is much more robust for soft-error immunity as compare to bulk. So anything that needs radiation protection (for example, military, aerospace – but those are not really the high-volumes), as well as automotive products, you’ll see value of better SER immunity as compared to bulk. Not just memory SER but logic SER. There are available design techniques to overcome / account for that. For example, if you design to overcome SER, you incur overhead in area for example. With FD-SOI, this is intrinsic, so you don’t need design tricks to suppress it.
ASN: When should designers consider using 28nm FD-SOI as opposed moving to 14nm FinFET or choosing another 28nm technology?
KL: By virtue of one being 28 and the other being 14, if you do need a lot of logic feature integration, or die-size reduction, 14nm will obviously become more necessary. If you just are looking for power savings, both 14nm FinFET and 28nm FD-SOI are fully depleted in nature, so both are able to operate with a lower power supply. So those are similarities. 14nm FinFET does provide higher performance compared to 28nm by virtue of how the process is constructed. Lastly, cost, which is related to the number of double-patterning layers – at 28nm, avoiding all the expensive double-patterning layers and 14nm having double-patterning being necessary for all the area scaling – that presents itself as a real difference. The end-product cost can also determine the choice of the technology selection.
Axel Fischer: The end-product cost, plus as well the investments from the customer side: the customer has to make a certain investment to develop the chip in terms of overall cost. If you look at photomask payment, NRE* and so on – this is weighting strongly, more and more as you go forward with advanced node technologies. There’s a set of customers that are feeling very comfortable to stay on the 28nm node.
KL: There are several 28nm flavors. There’s Poly-SiON, there’s HKMG, and there’s HKMG-FD-SOI. In terms of performance, there’s really a very clear distinction. In terms of power, you see a more radical power reduction with FD-SOI. In chip area scaling, I’d say roughly the same between HKMG and FD-SOI. This is dictated not so much by the transistor but by the overall design rules of the technology. So, 14nm is the higher cost point. 28nm is a much lower cost point, so overall a given budget that a customer has can determine whether 14nm is usable or otherwise. We have to sit down with the customer and really understand their needs. It’s not just trying to push one over the other solution. Based on their needs, we’ll make the proper recommendations.
ASN: Can designers get started today?
KL: We are moving FD-SOI discussions with customers to the next phase, which is to emphasize the design ecosystem readiness. So what we’ve been working on, and we really appreciate ST Micro’s support here, is to kick-start market adoption. We have access to ST Micro’s foundation library, and some of their foundation and basic IPs. Here, Samsung is distributing and supporting customers directly. They need to only work with us, and not with ST Micro. So they have access to the IP through us. We also provide design support, and we have additional IPs coming in to serve the customers from the traditional IP providers.
Many designers are new to body biasing. Fortunately, there are a couple of design partners that can help in this area. Synapse being one of them; Verisilicon another. Already, they have put in resources and plans and additional solutions to catalyze this market. In short, the PDK is available today, and the PDK supporting multi tools – Synopsys, Cadence and Mentor – are all available for download today. Libraries are also all available for download.
There’s nothing impeding designers from starting projects now. This is why we believe that 28FDSOI is the right node, because we are enabling the market to start projects today. If we start something else down the road, like a 14nm FD-SOI, for example, or something in between, the market will just say, hey, we like your transistor, we like your slides, but I have nothing to start my project on. So that is bad, because then it becomes a vicious cycle. We believe we have to enable 28nm designs now. Enable customers to bring actual products to the market. Eventually from there you can evolve 28 to something else.
ASN: Let’s talk some more about design considerations and body biasing, how it’s used and when.
KL: Both 14nm FinFET and 28nm FD-SOI are fully depleted. One unique technology value of fully-depleted architecture is the ability to operate the device at lower power supply. So power is the product of CV²/frequency. If you can operate this chip at lower power supply, you get significant dynamic power savings. FinFET does not have a body effect, so you cannot implement body biasing – it’s just not possible.
FD-SOI, on the other hand, has this extra knob – body biasing – that you can use. With reverse body bias (RBB), you can get much lower leakage power. If you want more performance, you can activate the FBB to get the necessary speed. Again, this is not possible with FinFET. So that will be one distinction. It depends on how you’re using your chip. It all depends on the system side, or even at the architecture side, how is it being considered already. If you’re already very comfortable using body biasing, then going to FinFET is a problem, because you’ve lost a knob. Some would rather not lose this knob because they see it as a huge advantage. That doesn’t mean you can’t design around it, it’s just different.
There are already users of body biasing for bulk. For customers that already use body biasing, this is nothing new. They’re pleased to now have the wider range, as opposed to the more narrow range for bulk.
AF: And probably going to FinFET is more disruptive for them. With FinFET, you have double-patterning considerations, etc. More capacitance to deal with.
ASN: Porting – does FD-SOI change the amount of time you have to budget for your port?
KL: If a customer already has products at 28nm, and they’re now planning the next product that has higher speed or better power consumption – they’re considering FinFET as one option, and now maybe the other option available is 28nm FD-SOI. The design learnings of going to FinFET are much more. So the port time will be longer than going to 28nm FD-SOI. We see customers hugely attracted because of this fact. Now they’re trying to make a choice. If it’s just a time-to-market constraint, sometimes FinFET doesn’t allow you to achieve that. If you have to tape out production in six months, you may have to use FD-SOI.
AF: Another key point for customers deciding to work with 28FDSOI is the fact that Samsung Foundry has joined the club. A few customers really hesitated on making the move to 28nm FD-SOI ST Micro is a very really advanced company, doing its own research and development, but the fact that the production capability was very limited has people shying away. Besides the technology, the presence and the engagement of Samsung is giving another boost to the acceptance.
KL: Yes, we’re recognized as a credible, high-volume manufacturing partner. That helps a lot.
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*NRE = non-recurring engineering. In a fabless scenario, there are NRE for IP and design (engineering costs, up-front and royalty-based IP costs), NRE for masks and fabrication (mask costs, wafer prototype lots, tools costs, probe cards, loadboards and other one-time capital expenditures), and NRE for qualifications (ESD, latch-up and other industry-specific qualifications, as in automotives).
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This is the second installment in ASN’s 3-part interview with Samsung on their 28nm FD-SOI foundry offering. If you missed the other parts, you can still read part 1 about technology readiness (click here), and part 3 on the ecosystem (click here).
ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 1, we’ll talk about technology readiness. In parts 2 and 3, we’ll talk about design and the ecosystem.
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ASN: Where does Samsung stand in terms of rolling out your 28nm FD-SOI offer?
Kelvin Low: We have completed key milestones. Wafer level qualification was completed in September 2014, and then product level qualification in March 2015. So, the good news is the technology is fully qualified now.
What we have additionally in terms of overall technology readiness is production PDKs available right now. We have run a couple of MPWs already, and we’re scheduling more for next year. Silicon is really running in our fab. I think many may not have grasped that fact. Silicon is running, and we are running production for ST as one of our lead customers.
Axel Fischer: We already have a long relationship with ST – since 32 and 28nm HKMG bulk. We had a press release where we stated that more than a dozen projects had been taped out. EETimes published an article at the time. Adding 28 FD-SOI was a natural extension of an existing relationship
KL: That’s right –This is not a new customer scenario – it’s an existing customer, but an expansion of technology. And, in this case, it’s also a collaboration technology and IP solutions.
We are ST Micro’s primary manufacturing partner; this is one reason that it’s mutually beneficial for both of us. Crolles is not aiming for high volume. They prototype well. They do MPW and IP well, but they are not a high-volume fab. So, we complete the production rollout at Samsung Foundry.
ASN: Do you have other customers lined up?
KL: The short answer is yes. Beyond ST, Freescale can we talk about, since they have openly stated that they are using FD-SOI with us. Other customers, unfortunately, we just can’t say.But, they are in all the market segments (especially IoT) where the cost and ultra-low power combination is a very powerful one.
ASN: What about technology readiness and maturity?
KL: We have a couple of different 28 variants: the LPP, the LPH with more than a million wafers shipped. And because of that, our D0 – defect density – is at a very mature level. 28FD-SOI, sharing almost 75% of the process modules of 28 bulk, allows us to go to a very steep D0 reduction curve. We are essentially leveraging what we already know from the 28 bulk production experience. Defect density is essentially the inverse of yield. So, the lower the D0, the higher the yield.
This slide [[see above]] show the similarities between our FD-SOI and our 28 HKMG bulk. You can see how more than 75% of bulk modules are reused. The BEOL is identical, so its 100% reused. On the FEOL, some areas require some minor tuning and some minor modification, but anything that is specific to FD-SOI is less than 5% that we have to update from the fab perspective. All the equipment can be reused in the fab. There may be a couple of pieces related to the FD-SOI process that need to be introduced.Other than that, the equipment is being reused and can depreciated,.which is essential for any business. We leverage another lifetime for the tools.
ASN: When will we see the first high-volume FD-SOI chips? Next year?
KL: It depends on what market segment. Consumer, yes, I fully agree, they can ramp very fast. But other segments like infrastructure, networking or automotive, they’ll take a longer time to just qualify products.
AF: It’s not just us. If our customer needs to prove that the product is compliant with certain standards, you have to go through test labs and so on, this can be a very lengthy process. Product can actually be ready, and we’re all waiting to produce, but they’re still waiting for reports and the software that’s goes on top – this can be a very long cycle.
KL: We’re already starting to support the production ramp for ST. They’ll be on the market very soon.
[[Editor’s note: ST has announced three set-top box chips on 28nm FD-SOI– you can read about them here.]]
KL: Everyone’s waiting for ChipWorks or TechInsights to cut away an end-product device that has FD-SOI. It’s just a matter of time.
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From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie-Noelle Semeria shares her insights here in part 2 of this exclusive ASN interview as to what Leti’s doing to drive the ecosystem forward. (In part 1, she shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)
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ASN: In which areas do you see SOI giving designers an edge?
MS: There is an advantage in terms of cost and power, so it’s attractive for IoT, for automotive, and more and more for medical devices. We see the first products in networks, in imaging, in RF. The flexibility of the design, thanks to the back bias gives another asset in terms of integration and cost. We consider that 28nm FD-SOI and 22nm FD-SOI are the IoT platforms, enabling many functions required by IoT applications. It’s a very exciting period for designers, for product managers, for start-ups. You can imagine new applications, new designs, and take advantage of engineered substrates combined with planar FD-SOI CMOS technology and 3D integration strategies to explore new frontiers.
ASN: What is Leti doing moving forward?
MS: Our commitment is to create value for our partners. So what is key for SOI now is to extend the ecosystem and to catch the IoT wave, especially for automotives, manufacturing and wearables. That’s why we launched the Silicon Impulse Initiative (SII) as a single entry gate providing access to FD-SOI IP and technology. SII is a consortium, gathering Soitec, ST, CMP, Dolphin and others, in order to beef up the EDA and design ecosystems. Silicon Impulse offers multi-project wafer runs (MPWs) with ST and GF as foundries based on a full portfolio of IPs. SII is setting up the ecosystem to make FD-SOI technology available for all the designers who have IP in bulk or in FinFET. To reach designers, we have set up events close to international conferences like DAC and VLSI, and we promote SII together with the SOI Consortium in San Francisco, Taiwan, Shanghai, Dresden….
The second way we are accelerating the deployment of FD-SOI technology in manufacturing is to provide our expertise to the companies who made the choice for FD-SOI technology. Leti assignees are working in Crolles with ST and in Dresden with GF to support the development of the technology and of specific IP such as back bias IP. The design center located in the Minatec premises is also open to designers who want to experiment with FD-SOI technology and have access to proof in silicon.
ASN: What role does Leti play in the SOI roadmap?
MS: The role of Leti is to pioneer the technology, to extend the ecosystem and to demonstrate in products the powerful ability of FD-SOI to impact new applications. Leti pioneered FD-SOI technology about 20 years ago. Soitec is a start-up of Leti, as well as SOISIC (which was acquired by ARM) in design. We developed the technology with ST, partnering with IBM, TI and universities. Now we’ve opened the ecosystem with GlobalFoundries and are considering new players. With the Silicon Impulse Initiative we are going a step further to open the technology to designers in the framework of our design center. We have had a pioneering role. Now we have to play a catalyst role in order to channel new customers toward FD-SOI technology and to enable new products.
Leti demonstrates that the FD-SOI roadmap can be expanded up to 7nm with huge performance taking advantage of the back biasing. Leti’s role is to transform the present window into a wide route for numerous applications requiring multi-node generations of technologies.
ASN: Is Silicon Impulse strictly FD-SOI, or do you have photonics, MEMS, RF-SOI…?
MS: We started with FD-SOI at 28nm because it’s available: it’s here. But as soon as the full EDA-IP ecosystem is set-up, this will be open for sure to all the emerging technologies: embedded memory (RRAM, PCM,MRAM…), 3D integration (CoolCube, Cu/Cu), imaging, photonics, sensors, RF, neuromorphic technology, quantum systems….which are developed in Leti. Having access to a full capability of demonstrations in a world class innovation ecosystem backed by a semiconductor foundry and a global IP portfolio leverages the value of SII.
ASN: Can you tell us about the arrangement with GlobalFoundries for 22nm FD-SOI? How did that evolve, and what does it mean for the ecosystem?
MS: Yes, last month we announced that we have joined GlobalFoundries’ GlobalSolutions ecosystem as an ASIC provider, specifically to support their 22FDX™ technology platform. We have worked with GlobalFoundries over the years in the frame of the IBM Alliance pre-T0 program..
In joining the GlobalSolutions ecosystem, Leti’s goal is to ensure that GF’s customers – chip designers – get the very best service from FD-SOI design conception through high-volume production. This has been in the works for a while. At the beginning of 2015, we sent a team to GlobalFoundries’ Fab 1 in Dresden to support ramp up of the platform. And now as an ecosystem partner, Leti will help their customers with circuit-design IP, including fully leveraging the back-bias feature, which will give them exceptional performance at very low voltages with low leakage.
We will be able to help a broad range of designers use all the strengths that FD-SOI brings to the table in terms of ultra-low-power and high performance, especially in 22nm IoT and mobile devices. It really is a win-win situation, in that both our customer bases will get increased access to both our respective technologies and expertise. It’s an excellent example of Leti’s global strategy.
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(This concludes part 2 of 2 in this Leti interview series. In part 1, Marie Semeria shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)
From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie Semeria shares her insights here in part 1 of this exclusive ASN interview as to what makes Leti tick. In part 2, we’ll talk about Leti’s new projects and partnerships.
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Advanced Substrate News (ASN): You’ve been CEO of Leti for a little over a year now, but those outside the Grenoble ecosystem are just getting to know you. Can you tell us a little about yourself and how you came to Leti?
Marie Semeria (MS): My background is in physics. I did my PhD at Leti on magnetic memories. Then I joined Sagem in the framework of a technology transfer, followed by a start-up in field-emission display (FED). When I came back to Leti, I spent more than 15 years in different positions, mainly involved in microelectronics. This work included setting up the cooperation with the IBM alliance and technology program coordination, as well as preparing Leti’s future and setting up long-term projects and partnerships.
Then three years ago the CEO at CEA Tech asked me to join that organization. CEA Tech is the technology research unit of the CEA (the French Atomic Energy and Alternative Energy Commission). Leti is one of CEA Tech’s three institutes, which together are developing a broad portfolio of technologies for information/communications technologies, energy, and healthcare. So I extended what I did in Leti covering the whole domain of expertise of CEA Tech. Finally, in October 2014, I took over from outgoing Leti CEO Laurent Malier.
ASN: Can you tell us about Leti’s structure and budget? How are you different from the other big European research organizations?
MS: Leti is a leading-edge research institute. Our mission is to innovate: with industry, for industry. So 83% of our budget comes from partnerships funded by industry, or partially funded by industry and supported by the European Commission or local or national authorities. The other 17% is a grant from CEA. Our commitment is to create value. And so the business model of Leti is value-centric – value for its partners.
ASN: How do you decide what you’re going to work on? Is it your customers?
MS: Leti focuses its work on technological research. We are not an academic lab. We work closely with industry. So we share our roadmap with our industrial partners, which gives us feedback on their expectations, their visions, and helps us anticipate their needs.
On another side, we have to be innovative ourselves, so we are very open to what is going on in the scientific world, sensing new trends, analyzing migrations, monitoring the emergence of new concepts. Therefore, part of Leti’s research is fed by partnerships with academic labs. And there are great opportunities to work with two divisions of CEA related to fundamental research in materials science and in life science. We have a partnership with Caltech in NEMS. We have partnerships with MIT, and with Berkeley in FD-SOI design. It is key for Leti to build on the relationships with the world’s leading international technological universities. We’re fully involved with the very active Grenoble ecosystem. There are great leveraging opportunities within MINATEC and MINALOGIC, with Grenoble-Alpes University and with the INPG engineering school in math and physics. The cooperation with the researchers at LTM is key in microelectronics and we will work with new teams at INRIA who will join us in the new software and design center located in MINATEC.
ASN: How much Leti activity is based on SOI?
MS: SOI is the differentiator for Leti in nanoelectronics. We pioneered the technology 30 years ago and boosted the diffusion and the adoption of the technology worldwide. This year we launched a new initiative named Silicon Impulse together with our partners ST, CMP, and Dolphin…to provide access to the FD-SOI technology and IP to designers. I would say about 50% of the resources of Leti is related to nano: nanoelectronics, nanosystems, nanopower, 3D integration, packaging, with silicon at the core.
All that we have developed in terms of CMOS, embedded memory, RF, photonics and MEMS, is based on SOI. So we’ve developed a complete, fully-depleted (FD) SOI platform for the Internet of Things, because you’ll need all these functions. Really, all the microelectronics activity of Leti has been based on SOI for a while now. It’s why today we continue to pioneer the technology. For example, we develop the substrates and we assess their performance with Soitec in the framework of a joint lab, which is a new strategy for both of us. We work with ST, with GlobalFoundries, to transfer the technology, to prove the substrate in their products. Now we are in a key position as a leading, innovating institute to turn our disruptive technology into products. So it’s really a turning point for us.
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Here’s a quick “official” summary of Leti:
As one of three advanced-research institutes within the CEA Technological Research Division, CEA Tech-Leti serves as a bridge between basic research and production of micro- and nanotechnologies that improve the lives of people around the world. It is committed to creating innovation and transferring it to industry. Backed by its portfolio of 2,800 patents, Leti partners with large industrials, SMEs and startups to tailor advanced solutions that strengthen their competitive positions. It has launched 54 startups. Its 8,500m² of new-generation cleanroom space feature 200mm and 300mm wafer processing of micro and nano solutions for applications ranging from space to smart devices. With a staff of more than 1,800, Leti is based in Grenoble, France, and has offices in Silicon Valley, Calif., and Tokyo. Learn more at www.leti.fr. Follow them on Twitter @CEA_Leti and on LinkedIn.
Click here to read part 2 of this exclusive interview.
This post was first published as part of Paul McLellan’s new Breakfast Bytes blog on the Cadence website.
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Cadence recently put out a press release that the Cadence implementation flow had been qualified on the GLOBALFOUNDRIES 22FDX process. At ARM TechCon, Joerg Winkler and Tamer Ragheb from the design enablement group of GLOBALFOUNDRIES in Dresden, Germany, provided a lot more detail. With German precision, their talk was titled The Implementation of ARM® Cortex®-A17 Quad-Core in GLOBALFOUNDRIES 22FDX Technology Using Cadence Innovus Implementation System. But I didn’t need to wait, I got a 1:1 meeting with Joerg earlier in the week and we went into more detail.
One thing that I had been confused about that Joerg clarified when I asked him is whether double patterning is used. I knew that the metal pitch was 80nm and so, in principle, could be single patterned. But that is only true if the layer is patterned in a single direction (vertical or horizontal but not both). For metal1 and metal2 they wanted to have both directions so that Ls and Ts could be made inside the standard cells, which meant that they needed to use double patterning.
At some level, the details of the process don’t affect the implementation flow that much. The transistors are inside the standard cells and other blocks, so whether they are planar, FinFET or FD-SOI is secondary to where the pins are, how the coloring affects placement, and so on. So the basic flow through Genus, Innovus and the various signoff engines is unchanged from any other process.
One area where FD-SOI is very different, as I went through in detail in my earlier blog, is the forward and reverse body bias (fbb/rbb). This is a voltage applied to the back of the thin buried oxide (the box) that doesn’t turn the transistor on or off (the box is too thick, and the bias can only change slowly due to the high capacitance). However, it does affect the performance of the transistor. This allows various tradeoffs: lower the voltage to reduce power, and then speed it up again with fbb; reduce leakage in a hibernating IoT device with rbb. Basically fbb increases the performance and this can be taken purely as increased performance, or as reduced power at the same performance. And rbb reduces performance but also decreases leakage, so it can be used when high performance is not required but power is critical.
The challenge that Joerg and his team faced was to come up with an architecture for how to connect up the bias. It is a little like planning a power grid. There are local decisions as to how to actually connect, what layer of metal to use and so on. Then there are block-level issues such as how to distribute the signals without creating huge blockages for routing. There isn’t really a chip-level issue like for power since, except perhaps for test chips, the bias is not expected to be externally applied through the package pins, but rather generated internally on the chips with charge pumps and enabled/disabled under software control. The highest level decision is to partition the chip into areas where different biases can be applied—the same bias is not needed everywhere.
The test vehicle chosen was a Quad-Core ARM Cortex-A17 processor. They decided to create five areas where the bias could be controlled independently, each of the four cores and then everything else, which notably includes the L2 cache and its controller. The libraries used were an 8-track standard cell library from Invecas (GF’s IP development partner) with continuous RX and support for body biasing. The cache memories were built from GF evaluation memory kit, with 14 different L1 cache memory macros, 1 L2 cache memory macro with support for body biasing of the bitcell array and for the memory periphery. An additional complication is that these areas also need to support power down (so cores can be powered off completely as well as biased). The body bias is all specified in the IEEE 1801 power file (so that all the other tools can handle the power policy chosen) and in the script that drives the Innovus Implementation System during physical design to actually create the connections.
The body bias nets needed to be connected up to dedicated pins on the well-tap cells, the power switches and the memory macros. The cells were carefully aligned so that the body bias connections were straight runs of metal, and then a body-bias net ring was placed around the perimeter of the module as is often done with power nets. See the diagram below.
The actual connections can be seen in the diagram below. The 10 yellow lines running across are the 10 body bias signals for the 5 regions (they are in pairs, one for P transistors and one for N). The green vertical lines in the middle pick up the appropriate pair of bias signals and these, in turn, are connected to the actual well tap cells (where the signals effectively connect to the back gate).
In a very similar way, the bias for the memory is also picked up from a ring and then run through the core of the memories using straight runs of metal.
GLOBALFOUNDRIES also created an implementation of the smaller ARM Cortex-A9 processor. They have been using this microprocessor for several technology nodes to allow a comparison of power, performance, and area (PPA). In this particular case they wanted to compare performance at different body biases compared to the 28SLP process. The result is that 22FDX with fbb has 30% higher frequency at the same power (along with a 45% area reduction) and with rbb has 45% power reduction at the same frequency (and obviously the same 45% area reduction). This means that the implementation can vary over a huge range of power/performance with the same silicon, whereas at 28nm it would require a complete re-implementation (which is why it appears as a single red dot rather than a curve).
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This post was first published under the new Breakfast Bytes blog on the Cadence website. The original is here. Many thanks to the folks at Cadence and to Paul McLellan for permission to repost it here on ASN.
New approaches in chipmaking and fast-evolving specialty markets are driving the need for new equipment on the fab floor. 3D chips (be they stacked or bonded), MEMS, lighting, power – they’re all leveraging wafer substrates in new ways. Altatech, the equipment division of SOI-wafer leader Soitec, has just announced new inspection equipment for foundry and IDM customers fabbing 3D and other chips. ASN talks to Jean-Luc Delcarri, Altatech general manager, about the company and its recent announcements.
Advanced Substrate News (ASN): Can you tell us briefly about the company and the markets it serves?
Jean-Luc Delcarri (JLD): Altatech makes specialty equipment for the fab floor. We have two main areas of deep expertise: one is in defect inspection, and the other is in CVD* technologies for semiconductor, LEDs, MEMS and photovoltaic devices. I founded the company in 2004, and then in 2012 we became a subsidiary of SOI wafer leader, Soitec.
ASN: At Semicon Europa 2015, you announced “…a new, high-speed inspection system for ultra-thin, transparent and bonded substrates inspection for 3D applications in power, MEMS and mobile technologies.” What’s driving that market?
JLP: Yes, at Semicon we announced the Eclipse TS, which is a unique, high-reliability and easy-to-implement inspection system solution that’s now ready for mass production.
You’ve got the need for these advanced substrates that’s being driven by really rapidly growing markets in automotive, industrial power and mobile electronics. We’ve been working quietly on this tool for years, and now the Eclipse TS has been qualified for volume manufacturing at a leading-edge semiconductor manufacturer, so we’re really excited about it.
ASN: What makes the Eclipse TS different from other inspection sytems?
JLP: When you’re looking for defects on these advanced wafer solutions, you have to do much more than scan the top: you need to inspect the front side, the back side and the edge of very thin wafers – and you have to do it without touching them. Our ability to do all this makes us totally unique on the market: we have built this tool on a strong IP portfolio.
So with the Eclipse TS, you have a high-speed inspection system that can measure very thin and stacked wafers down to 50 microns, as well as Taiko rings, stacked substrates and silicon-on-glass wafers. Plus we can do the front-side, back-side and edge inspection in one pass with no back-side contact.
In today’s 3D technologies, substrates undergo grinding, stacking and gluing, so you can end up with wafers with a very high bow, or wafers with a warp of up to 6 mm. We can handle those wafers. In fact, the Eclipse system can monitor these sorts of processes. The inspection occurs without any contact on the active surface, and at a throughout of more than 90 wafers per hour for 300-mm substrates.
We’re of course compliant with the latest automation standards, so the system can be fully integrated into the line, and provide comprehensive reporting for defects classification and yield maps.
Our full Altatech Eclipse series covers advanced metrology and holistic inspection systems. That means we can detect, count and bin defects during the wafer manufacturing process as well as do continuous outgoing wafer-quality inspection. So the quality of both the wafer-surface and edge is ensured. We also have proprietary Eclipse sub-modules that detect specific sorts of particles and defects of interest for both patterned or unpatterned wafers.
All that puts Altatech in a leading position in what is a very large market opportunity.
ASN: You also make CVD – deposition – equipment. Can you tell us a little about that, and what’s driving those markets?
JLP: Sure. Last year we introduced the AltaCVD 3D Memory Cell™, which is the newest member of our AltaCVD product line. This is used for depositing ultra-thin semiconductor films when you’re manufacturing the high-density, low-power memory chips used throughout mobile electronics. Our new system does atomic-layer deposition 10 times faster than conventional ALD** systems, which is of course huge when you’re manufacturing advanced memories where you need to run in very high-volume production with extreme cost efficiency.
In the new 3D device architectures for mobile apps, our customers are looking to really increase memory capacity and boost performance. And to do this, they need very advanced material deposition to create atomic-layer films with high uniformity – you really are at the atomic level of control here. The AltaCVD 3D Memory Cell deposits layers of chalcogenide*** materials by using a combination of precursors, which is very leading edge.
So with our tool you can use conventional gaseous or solid precursors, but we also have a patented pulsed technology, which means you can also use advanced CVD precursors that are available only in liquid form. This is remarkable versatility: it allows us to achieve exceptional step coverage over features with very high aspect ratios – that’s a key performance requirement when you’re talking about vertical integration high-density memory circuits.
You can also use it for advanced pre-treatment of semiconductor surfaces (which improves circuit functionality), as well as post-treatment of surfaces (which enhances electrical performance).
Because it’s used in everything from research to high-volume manufacturing, it can process 200-mm or 300-mm substrates, and uses a single-wafer, multi-chamber architecture. One of our key customers demonstrated it last year. We’re now selling production units, and we’re pleased to say it’s been very successful.
ASN: Do you have other products in the pipeline?
JLP: Next up we have a new solution for high aspect ratio 3D copper deposition. The system, which is called RUBY, can deposit a barrier layer of titanium nitride or tantalum nitride with almost 100% step coverage on an aspect ratio higher than 10:1. This is followed by deposition of a copper seed layer with similar performance. Combined with a proprietary copper cleaning process, it will be able to meet the growing challenge of copper metallization in MEMS and semiconductor 3D integration. We’ll release it as soon as we’ve completed our product milestones for reliability and performance.
ASN: Where do you see the highest-growth areas?
JLP: We’ve developed the right technology for the right time in a number of key markets, so we’re really well-positioned to answer the needs of a number of high-growth markets. The move to 450mm wafers is something we’re ready for, which will probably happen first in advanced memories. But in the meantime we also see significant activity in MEMS, RF, high power and LEDs. We’re winning customers in China who are looking to be leaders in these markets. All in all, much of the future of the phone in your pocket depends on what we can help our customers do in high-volume and cost-effectively on the fab floor – so it’s a very exciting time to be in this business.
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*CVD=chemical vapor deposition
**ALD=atomic layer deposition
*** chalcogenides include sulphides, selenides, and tellurides
With five manufacturing sites around the world and 72,000 wafer starts/month, X-Fab is a leading pure-play analog/mixed-signal and specialty foundry for automotive, industrial and medical applications. ASN recently had the opportunity to talk to Tilman Metzger, Product Marketing Manager for the X-Fab Group, about when customers choose an SOI-based offering.
Advanced Substrate News (ASN): Can you give us an overview of the SOI offering at X-Fab?
Tilman Metzger (TM): X-FAB offers a range of SOI solutions from 1µm to 0.18µm. We support high voltage (HV) requirements from 20V to 650V. X-FAB also targets very high temperature applications of up to 225˚C.
Our latest addition to the SOI family is XT018, our first 0.18µm SOI solution. The modular XT018 platform combines a state-of-the-art 180nm mixed-signal process with benefits of a robust SOI HV technology. XT018 supports voltages up to 200V and targets next generation automotive and industrial applications.
ASN: When did X-Fab first start offering SOI and why?
TM: We started more than 15 years ago with a 2µm HV SOI process. Our first SOI development was driven by specific customer requirements for an HV motor driver application.
ASN: What sorts of chips are currently being manufactured by X-Fab using SOI?
TM: X-FAB solely focuses on analog and high-voltage SOI applications. We do not target RF-SOI or high density SOCs like CPUs etc.
Typical products include high-side gate pre-driver ICs, motor driver ICs, ultrasound driver ICs, solid state relays, optocoupler and analog switch arrays.
ASN: For X-Fab, what are the traditional SOI markets (both in terms of end-markets and geography)? How do you see it evolving?
TM: Historically, we have seen demand for SOI-based technologies mainly from the industrial sector. That said, we expect to see more automotive customers adopt our SOI solutions in the future.
Geographically, our SOI customer base mostly originates from North America, Europe and Japan. Customers from Greater China and South Korea are generally slower in adoption but gaining momentum.
ASN: When and why do your customers choose an SOI-based process?
TM: Typically, we see two types of SOI customers:
ASN: Can you expand on the time-to-market (TTM) issue a bit?
TM: Since SOI substrates are more expensive than normal bulk wafers, the average wafer price is also higher. Typically customers look at a straight cost-per-die calculation when evaluating the business case for their product. But there’s also the aspect related to ease of design – with SOI, design is easier, so the design cycle might be faster and less costly in terms of engineering time. As a result, if customers can launch their product faster, they can grab more market share and increase their profits.
ASN: What kind of support do you offer designers for SOI-based chips? Is it different from the sort of support for bulk processes?
TM: Generally, for our SOI technologies we offer the same comprehensive support as for our bulk solutions. In addition, we provide SOI application notes that discuss SOI related design considerations. With the exception of XI10, the SOI material we are using is “thick film” SOI, where the device layer is up to 55µm thick, so the behavior of active devices is similar to those on non-SOI substrate. Let’s consider the designers doing high-voltage analog: in bulk, they do standard junction isolation, but in SOI they use deep trench isolation, which actually comes with fewer parasitics, so it’s easier to simulate and design.
ASN: Would you say the SOI ecosystem is well established in the markets X-Fab serves?
TM: There are no special SOI ecosystem requirements for X-FAB’s SOI solution. We use established SOI wafer suppliers and support all major EDA platforms (Cadence, Mentor, Synopsys, Tanner). with complete design kits. Analog and high voltage is all about customization. In the analog world, there are some generic IPs, but most of it is specialized. We offer basic IPs for SOI solutions including I/O and standard cell libraries and memories such as OTP, SRAM etc. which is similar to our offering for non-SOI processes..
ASN: Can you tell us more about X-Fab’s SOI offerings?
TM: X-Fab has two one-micron SOI ultra-high-voltage process offerings for 650 Volt and 350 Volt which are used by customers for applications that plug directly into the grid. There is also a big market for 600V IGBT and MOSFET driver ICs. Some customers select these processes for their inherent robustness in applications like avionics and aerospace. (We do not offer specific radiation-hardened solutions, but our customers use these when they have particular reliability requirements.)
Our one-micron process XI10 targets very high-temperature applications: it offers different metallization schemes, and can support up to 225°C.
XT06 is a 0.6µm SOI technology that supports voltages up 60V and is popular across a range of industrial applications.
XT018 is our latest SOI solution. As mentioned earlier it not only targets industrial and medical applications, but also next generation automotive products. An example is the new CAN FD** standard which is more complex and challenging to implement. XT018 offers the right process options to address these requirements. X-FAB has a long successful track record of serving the automotive market. This is also reflected by the fact that the automotive segment accounts for more that 50 percent of our total revenue.
ASN: For MEMS, when and why do your customers opt for an SOI-based solution? Do you see any growth in interest in putting MEMS on SOI?
TM: For MEMS, we definitely see the opportunity to take advantage of SOI material. In general, SOI wafers are interesting for the formation of highly uniform silicon membranes or other mechanical structures, especially if we prefer to use SOI’s mono-crystalline properties rather than depositing poly silicon. The top device layer is ideal for defining silicon features with thicknesses from a few microns to several tens of microns, without the effort of very long silicon deposition times. The buried oxide (BOX) layer acts as a natural etch-stop layer during silicon etching, at the etching either from the front or from the back of the wafer. Stopping at the BOX layer mitigates any non-uniformity for the deep silicon etch and allows for great process control.
For instance, at X-FAB, we use SOI wafers to manufacture our open-platform gyro sensor / accelerometer process. We use the SOI wafer’s device layer to make single-crystal masses with uniform thickness for predictable and robust performance. In this case the buried oxide layer not only acts as an etch stop when etching the silicon but is also a sacrificial material to remove from underneath silicon structures such as inertial masses and comb-drives.
We also have our newer three-axis gyro / accelerometer process where X-FAB is making its own SOI substrate with buried cavities. In other cases, we etch a pattern all the way through the back side of the wafer to leave thin membranes on the front side of the wafer. Again, the etch is well-controlled, stopping on the buried oxide and the remaining oxide / device layer silicon membrane could be used on its own or with further layers and structuring to form a variety of device types such as pressure sensors, force sensors, thermopile structures or microphones.
ASN: Do you see SOI becoming a more important part of X-Fab’s offering? If so, why?
TM: Yes. One of the factors that we foresee to drive SOI based designs is the increasing challenges of automotive systems and ICs. This is largely driven by newer standards like CAN FD. While SOI is is still a relatively small part of our business, we see opportunities, especially with our XTO18 offering, which may open new high-volume markets.
We have customers that require a stable supply of their product over a long period in time, often for a decade or more. In the automotive industry, those customers are using a 10-year old process. We need to be able to guarantee that those processes will be available for ten to fifteen years.
We have customers in consumer markets using SOI – either because they’ve tried and failed on bulk, or they’re looking for long-term solutions. They see the benefits in the ease and speed of design, which helps them ensure that they don’t miss windows of opportunity. But they need to crunch the numbers themselves. SOI will give them a smaller chip size, but there is not a “one fits all” approach – it depends on the design topology.
ASN: Will the SOI-based processes offered by X-Fab evolve? If so, how and why?
TM: Remember, analog and mixed-signal is not a linear shrink like for digital. The node at 0.18 microns is the leading edge for high-voltage. We can add more functionality and more voltage classes. We’ll continue to add features and modules where we see opportunities for increased performance or new markets. That said, for the five platforms in our current SOI offering, the mature ones won’t change too much except for increasing performance. The markets are evolving, but they’re also very conservative.
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X-Fab has organized a series of design webinars, including a number that cover SOI-related topics. Click here to access the list.
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* EMI = electromagnetic interference; EMC = electromagnetic compatibility; ESD = electromagnetic discharge
**CAN stands for controller area network, a protocol that allow microcontrollers and other devices to communicate without a CPU. It is used extensively in automotives for connecting electronic control units (ECUs) and in industry for factory automation. CAN FD is CAN with Flexible Data rates.
A driving force in FD-SOI, Leti recently announced a service called Silicon Impulse®, a new FD-SOI platform for IoT & ultra-low-power (ULP) apps that helps start-ups, SMEs and large companies evaluate, design, prototype & move to volume. Olivier Thomas, who’s in charge of the program and Ali Erdengiz, who’s Business Development Manager for Leti explain how it works.
Advanced Substrate News (ASN): What exactly is Silicon Impulse? What services does it offer?
Olivier Thomas (OT): Silicon Impulse provides design services from emulation to test program development and qualification (emulation, advanced building blocks and IPs access, full control design flow, industrial MPW, packaging and board, test and qualification).
So you can consider Silicon Impulse as a silicon enablement and development platform: a unique IC prototype development and production hand-off partner for companies in need of the latest low-power semiconductor technologies and heterogeneous integration solutions (FD-SOI, BEOL NVM, MEMS, 3D…). We work with a strong network of industrial partners and offer a single entry point along product maturation.
Silicon Impulse leverages Leti’s* and List’s** expertise as well as top industrial partners belonging to a global network of experts in analog, RF, digital and memory design, as well as hardware/software-integrated solutions.
In a nutshell, Silicon Impulse offers:
[Editor’s note: Click here to download the Silicon Impulse brochure.]
ASN: Who is it aimed at?
Ali Erdengiz (AE): We saw that the increasing cost of leading semiconductor technologies, the level of expertise, tools and resources required to develop innovative products using such advanced processes can make it really challenging for new entrants (product and solution innovators). So CEA Leti created the Silicon Impulse initiative to help innovative companies to get their projects off the ground. We provide an advanced silicon development platform, help them develop their IC and/or subsystem and then hand it off to the production supply chain.
We did this because we see that today’s new markets are driven by a variety of applications and new players – it’s not just the big players scaling for PCs and mobiles anymore. IoT is a great opportunity for the emergence of innovations and ideas from new entrants. We’ve been getting more and more requests from partners looking to integrate the advanced technologies developed in Leti such as BEOL NVM and MEMS. They’re thinking outside of the box, so they are also interested in using 28nm FD-SOI while requesting advanced features and specific performance at low-voltage. Leti has always done technology research. Now with Silicon Impulse we provide a new service in collaboration with other industrial partners to help companies evaluate, design, prototype, and launch their products.
ASN: If FD-SOI design is so easy and so close to what designers have done in bulk, why do they need this sort of service?
OT: Indeed, one can easily migrate from bulk to FD-SOI and benefit immediately from its low power/low leakage characteristics. However, we’ve seen that many of the companies that port their circuits to FD-SOI don’t exploit the full potential of the technology. Silicon Impulse leverages Leti’s strong expertise and experience in FD-SOI technology from device to Digital/RF modeling and advanced design solutions and maximizes the gains of the technology. Our competence center provides its industrial partners with quick access to information, know-how and silicon proven advanced design and architecture solutions to efficiently manage performance, power consumption and process variability. Here are some examples: PVT sensors, timing fault tracking, control theory module (i.e. algorithm to figure out the optimum energy point), fast feedback loop on the top of tailored charge pump and other blocks to back bias efficiently.
In addition, Leti’s Silicon Impulse’s expertise is not limited to designing FD-SOI IC’s. Leti brings a wealth of system knowledge and application know-how from device technology through embedded software that ensures full success and differentiation for its partners’ projects.
ASN: Why should designers consider FD-SOI?
OT: The 28nm/22nm technology nodes are seen as a long-lived technology node and a sweet spot for performance, power and cost. FD-SOI is optimized for low-voltage, low-power applications that can nevertheless need high performance.
For digital design, the extended range (+/-2V) of back biasing along with PVT sensors, timing fault tracking, theory control module and fast feedback loops controlling the back bias enable efficient process compensation and energy optimization for a wide range of applications (E. Beigne et al. ISSCC’14).
For SRAM design, the un-doped planar technology offers a large portfolio of SRAM bit-cells (High-density, Low power, High-performance) enabling very good performance over a wide voltage range. The Single P-Well bit-cell architecture combined with a wide back bias range enables both low operating voltage and fast access time. In sleep mode, the back bias can be set to minimize the bit-cell standby leakage current and the data retention voltage (O. Thomas et al. IEDM’14).
For RF design, one key aspect shown in the paper presented at ISSCC 15 is the continuous re-configurability through VT adjustment by the back-gate. The Power Amplifier discussed in the paper can pass from a high-linearity/high-efficiency state to a high power state by continuous linear tuning; something that cannot be done in other technologies. At the same time, the 28 FD-SOI allows designers reach much higher FT/Fmax than bulk. The result is higher available gain in mm Wave (as shown in our example at 60GHz). This approach drastically reduces the PA’s power consumption in 90% of the use cases, thus enabling WiGig for example in mobile applications.
ASN: What are the logistics for getting started?
OT, AE: Silicon Impulse can help innovators with their projects from concept through production hand-off. To get started on a project, we do a business review to determine where and how Silicon Impulse can contribute. We can provide architectural advice and shape the product from a very high level, develop a feasibility study and make recommendations as to how to implement the system. Leti and its partners can provide unique IP and/or technology components such as foundation IP or more complex system level IP blocks, RF, MEMS, 3D components and any other advanced technology to shape a truly unique and advanced yet manufacturable product. Another layer of contribution of Leti, List would be in providing embedded software to complete the whole product. So Silicon Impulse’s involvement can be limited to architectural consulting or extended to developing and delivering the whole system or anything in between.
ASN: You’re running multi-project wafer (MPW) shuttles – can you tell us more about that?
OT: Leti offers its MPW shuttles to open the doors to a wider set of users and projects (some of whom might not have access to or be ready yet for full service foundries). An MPW shuttle serves two main purposes:
However, we’ll also be making an announcement in the near future with details of schedules for planned MPW shuttles with our industrial partners.
ASN: How long will it take to get to a working design?
AE: This is project dependent, but leveraging Leti’s experience and already proven IPs and methodologies it is likely that our partners will develop a successful design even faster than if they did it on their own regardless of whether they used FD-SOI or bulk. Using FD-SOI for digital design targeting low power without compromising performance will certainly get you there faster than using bulk. In addition, the intrinsic characteristics of FD-SOI and much better control of device variability will accelerate analog and RF design and reduce time to market.
ASN: Will the design then be transferable to a full-service, high-volume fab?
OT: The purpose of Silicon Impulse is to ease IC prototype development and enable/accelerate production ramp-up. Silicon Impulse completes the Leti R&D offering by transferring the technology into a manufacturable product. The production is then handed off to a full service fab and/or supply chain partner. We’ll begin announcing the names of these partners shortly.
For information on contacting Leti’s Silicon Impulse service, click here.
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Olivier THOMAS is the project leader of Silicon Impulse for Leti. He received the M.S. Electrical Engineering degree from ISEN in 2001 and the Ph.D. degree from the Telecom ParisTech in 2004. He joined the CEA-LETI Laboratory in the Center for Innovation in Micro & Nanaotechnology (MINATEC), Grenoble, France in 2005. From 2005 to 2014 his research work was focused on advanced low-power digital and memory design in leading edge SOI technologies (PDSOI, FDSOI) and heterogeneous technology co-integration (ReRAM, 3DVLSI). From 2010 to 2012, he was a visiting researcher at Berkeley Wireless Research Center (BWRC) of University of California at Berkeley. He worked on methodologies to characterize on large-scale static/dynamic SRAM performances. From 2012 to 2014, he launched and led the Leti’s advanced memory design activity. He is author or co-author of 75 articles in international refereed journals and conferences and 25 patents.
Ali Erdengiz is Business Development Manager for Leti/List. He has spent 20 years in Silicon Valley and held various engineering, marketing, product and business unit management functions at companies such as ST Micro, National Semiconductor, Fujitsu, Altera, Abound Logic and eSilicon. Ali holds a BSEE from ESME, an MSEE from Université Parix XI and an MBA from San Jose State University.
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*CEA-Leti is a research-and-technology organization with a large and word class expertise from device through system integration. It specializes in nanotechnologies and their applications. NEMS and MEMS are also at the core of its activities. Leti is capable of not only developing semiconductor devices (analog, mixed-signal, RF, digital, MEMS) but also integrating them into subsystems using PCB, MCM, 2.5D and 3D technologies as well as developing embedded and application software to deliver full system level solutions.
**A sister organization to CEA-Leti, CEA-List conducts R&D in fields that create value for the economy and society. As such, the primary mission is to give businesses the tools they need to turn their innovative ideas into marketable products.